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DRAM is following NAND in going 3D, but architecture needs are unique and challenging. 3D DRAM is needed to keep up with the demands of graphics cards, portable devices, and more. Here's an idea of how to architect it.
newsroom.lamresearch.com
An interesting article to read through for those who haven't been keeping up with all the latest on 3D-DRAM process integration or architectures
The capacitors and access transistors they propose would appear to require lithography for every layer. This is not impossible of course, but if they are doing that many other things can be done without the complex etching.
To be fair LAM is an etch and dep company who wants to sell their new toys. As for the litho situation, complex dep/etch with multiple simple litho passes is more preferable than something crazy like EUV SAQP/SALELELELE. As for other architectures forgive my ignorance, but are you talking about some architecture where you stack multiple layers of hybrid bonded 2D DRAM (in a similar manner to sequential CFET)?
To be fair LAM is an etch and dep company who wants to sell their new toys. As for the litho situation, complex dep/etch with multiple simple litho passes is more preferable than something crazy like EUV SAQP/SALELELELE. As for other architectures forgive my ignorance, but are you talking about some architecture where you stack multiple layers of hybrid bonded 2D DRAM (in a similar manner to sequential CFET)?
I don't understand your meaning here Fred. Are you saying they should have done something more like 3D-NAND? Or are you saying this architecture is more 3D nand like than Tanj was indicating? If it was the former, I don't disagree that this would be ideal (as I think 3D NAND is the most genus/elegant solution to scaling challenges this industry has ever come up with). However I don't know how you would go about forming DRAM arrays in one litho pass like you do with NAND. If I did, I wouldn't be working in the logic side of the industry, and I would be making alot more dough.
I don't understand your meaning here Fred. Are you saying they should have done something more like 3D-NAND? Or are you saying this architecture is more 3D nand like than Tanj was indicating? If it was the former, I don't disagree that this would be ideal (as I think 3D NAND is the most genus/elegant solution to scaling challenges this industry has ever come up with). However I don't know how you would go about forming DRAM arrays in one litho pass like you do with NAND. If I did, I wouldn't be working in the logic side of the industry, and I would be making alot more dough.
To be fair LAM is an etch and dep company who wants to sell their new toys. As for the litho situation, complex dep/etch with multiple simple litho passes is more preferable than something crazy like EUV SAQP/SALELELELE. As for other architectures forgive my ignorance, but are you talking about some architecture where you stack multiple layers of hybrid bonded 2D DRAM (in a similar manner to sequential CFET)?
No, I was talking about what you say, multiple simple litho passes. I did work out a way to do that, it looks like you can do fairly simple litho to get about 4Gb/cm2 per layer and then deposit layers. The tricky part is to get successive layers of good crystal, but there is a way to do that too. The result is probably a little cheaper than today's DRAM but a lot denser and likely faster too, since the bit lines are quite short and can be built with low RC.
You can form the capacitors easily enough, assuming trenching is used for the outlines separating them after forming them with uniform layers, but it is not clear how you would build the access transistors and word lines without litho steps on each layer. Also, it is tricky to get good crystal for the access transistors if you need to include dielectric layers sandwiching the silicon core layer.
You can form the capacitors easily enough, assuming trenching is used for the outlines separating them after forming them with uniform layers, but it is not clear how you would build the access transistors and word lines without litho steps on each layer. Also, it is tricky to get good crystal for the access transistors if you need to include dielectric layers sandwiching the silicon core layer.
I am much more impressed not with how they stacked capacitors, as it's only that many ways you can stack them physically after all, but with how they carved bitlines. And I am sure they are not disclosing much of critical details.
newsroom.lamresearch.com
