Intel 10nm+ features presented at IRPS 2020

[Fred Chen]

At IRPS 2020 (April), Intel revealed the changes made with 10nm+ compared to original 10nm: an 11th metal layer after M10, and denser MIM capacitor. Everything else the same. Gate patterning same as their M0 and M1 oddly enough (SAQP). If you would like a copy, let me know. R. Grover et al., A Reliability Overview of Intel's 10+ Logic Technology.

 

[Jumper]

At IRPS 2020, Intel revealed the changes made with 10nm+ compared to original 10nm: an 11th metal layer after M10, and denser MIM. Everything else the same. Gate patterning same as their M0 and M1 oddly enough.

Do you know how does that change performance or does it just improve yields?

 

[Fred Chen]

Do you know how does that change performance or does it just improve yields?

The paper focused on reliability assessments like TDDB. No comparison with prior 10nm was shown.