How hard is 2.5D and 3D advanced packaging from an equipment prospective

[Andy1299]

I know the chief difficulty is designing each die ahead of time for future 3D packaging (Zen 3D for example). However, I was wondering how difficult leading-edge hybrid CU and direct CU 3D packaging is from an equipment perspective? Is it more on the difficulty level of deposition and etch (i.e. many companies have suitable tools) or is there an ASML of advanced packaging? who are the leading players here? (K&S, Be Si etc..) I've enjoyed reading about and understanding how difficult EUV is but there seems to be much less out there on advanced packaging equipment.

***former Physics/ EE post grad****

 

[Jert]

In general, 3D packaging's processing feature sizes are huge (in microns vs in nanometers in actual leading edge logic devices). So ASML does not play a role in this space (or at least EUV is not needed, and will never be needed). Instead, lithography equipment handling bigger features but with higher productivity, like from Ultratech (now part of Veeco) are often used. For deposition and etch, the feature sizes (and more importantly the aspect ratios) are no more challenging than those already being used in 3D NAND devices today, so equipment and capability already exist in the industry, in general.

 

[Andy1299]

In general, 3D packaging's processing feature sizes are huge (in microns vs in nanometers in actual leading edge logic devices). So ASML does not play a role in this space (or at least EUV is not needed, and will never be needed). Instead, lithography equipment handling bigger features but with higher productivity, like from Ultratech (now part of Veeco) are often used. For deposition and etch, the feature sizes (and more importantly the aspect ratios) are no more challenging than those already being used in 3D NAND devices today, so equipment and capability already exist in the industry, in general.

Thanks, was asking a slightly different question: who are the leading players set to benefit from 3D packaging? E.g., K&S or be semiconductors or someone else? And how differentiated are they? (Or said another way how difficult is building the needed equipment)

 

[Paul2]

Thanks, was asking a slightly different question: who are the leading players set to benefit from 3D packaging? E.g., K&S or be semiconductors or someone else? And how differentiated are they? (Or said another way how difficult is building the needed equipment)

The biggest benefactor from 3D is actually "legacy," low volume asic, MCUs, and of course memory (stacking.)

It's basically all about having decently fast, and power efficient SRAM/MRAM/DRAM/FLASH without paying an arm, and a leg for memory space on a logic process.

 

[count]

In terms of 3D packaging, my understanding is the tooling and equipment is far less complex and far more standardized than say lithography. I can't think of any company in particular that is a real winner here from a supplier perspective, but I could be wrong.

 

[Jert]

In terms of 3D packaging, my understanding is the tooling and equipment is far less complex and far more standardized than say lithography. I can't think of any company in particular that is a real winner here from a supplier perspective, but I could be wrong.

Very much agree. 3D packaging technology, at least for now, is scattered amongst companies. No dominant sector winners similar to apple, tesla, tsmc. From the fab side, tsmc develops its own packaging for its foundry customers, sony does its own for their advanced image sensors, various memory makers also try to do stacking/3D packaging to improve its value, as well as the traditional packaging companies ASE, Amkor, etc. From the equipment/materials supplier side, it's essentially the same players that also supply the fabs front end processing needs.

 

[mgoldsmith1979]

The kind of hybrid bonding SoIC and similar packaging uses is a thermal-compressive bonding of two dice, using copper pillars. As stated above, all of that is printed with very old tools and in the upper metal pitch layers (where you might not even use 193i), so basically any of the folks in the stepper space would benefit. Now, for alignment of wafers and improved overlay, there will be specific machines that support this, but again no one owns that market as it isn't as extremely cost-prohibitive to do like EUV was.
In terms of IP ownership, Xperi / Tessera / Invensas have IP covering DBI formation and assembly, and you will see most every Foundry or OSAT has already partnered with them for this process, so I don't think there is much cheese down the hole in that sense either. I you want broad exposure to the semi players look at SMH or similar ETFs instead of a single company / player.

 

[Andy1299]

The kind of hybrid bonding SoIC and similar packaging uses is a thermal-compressive bonding of two dice, using copper pillars. As stated above, all of that is printed with very old tools and in the upper metal pitch layers (where you might not even use 193i), so basically any of the folks in the stepper space would benefit. Now, for alignment of wafers and improved overlay, there will be specific machines that support this, but again no one owns that market as it isn't as extremely cost-prohibitive to do like EUV was.
In terms of IP ownership, Xperi / Tessera / Invensas have IP covering DBI formation and assembly, and you will see most every Foundry or OSAT has already partnered with them for this process, so I don't think there is much cheese down the hole in that sense either. I you want broad exposure to the semi players look at SMH or similar ETFs instead of a single company / player.

Thanks for the very knowledgeable reply