I recently learned that the first HKMG DRAM only entered HVM relatively recently, having scanned some IEEE papers from the early finFET era they just say that HKMG would make for stronger lower power DRAM (duh) and that it would require alot of work. More recent papers make a big deal of "DRAM compatible" HKMG schemes. For anyone on this forum was/is clued into the world of DRAM, why did it take so long to move to HKMGs? If my understanding is correct they already etch fins and use the surface along the side/bottom between the two fins as the channel (as opposed to logic which uses the fins themselves as the channel), and there is a move towards vertical nanowire transistors underway for DRAM. If the DRAM industry could adopt these different higher performing/lower leakage transistor architectures, how could they have only just now started reaching HKMGs at 1x? What about DRAM nodes made them incompatible with gate last HKMGs prior to the 1x/y nodes from Samsung?
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