GENIOTM Co-Design EDA Tool Now Includes Parasitic Estimation and Stack Planning Functionalities. GENIO 1.6 Significantly Reduces Advanced Systems Total Design Time and Complexity.
Rome – January 18, 2022
GENIO 1.6 Significantly Reduces Advanced Systems Total Design Time and Complexity
MZ Technologies today unveiled GENIO Version 1.6 that now includes Parasitic Estimation and Stack Planning functionalities to further slash total design time and reduces overall design complexity.
GENIOTM remains the only integrated-from-the-ground up chiplet-packaging Co-design EDA tool and the addition of the two new functions further increase its ability to meet 2.5D and 3D advanced packaging design challenges.
Parasitic Estimation enhances GENIO’s time-to-design superiority. This function enables early-on system analysis, based on virtual routes, prior to physical implementation. Parasitic Estimation is usually implemented after a chiplet-based system design and its system-level interconnects have optimized end-to-end 3D-aware signal assignment.
GENIOTM produces a pre-routing Parasitic Estimations report, based on Manhattan distances and coupled with RC and TSV/bump/C4/balls contributions, to enable early-on Static Timing Analysis. The key value is the ability to conduct static timing analysis during system exploration without waiting the results of the lengthy detailed physical routing process.
The Stack Planning Support helps designers automatically identify the best possible 3D stack configuration, given physical and electrical constraints. The new floor planning methodology provides a more efficient chiplet-based 3D-IC system organization, optimizing electrical performances and reducing the physical resources (TSVs) required for vertical interconnect.
Stack Planning provides a detailed comparison of multiple floor planning scenarios that allow the early comparison of multiple architecture configurations.
Floor plan configurations are tagged and compared. Connectivity Status dialog displays net lengths/statistics and can be filtered by Net Name, Net Group, path, sub-paths.
New 3D stack planning features are specifically designed to setup system initial configuration, improve exploration of all possible configurations, optimize and compare the most promising ones and finally suggest the optimal final solution.
In addition, Stack Planning improves manufacturability design efficiency by automating 3D-IC exploration focusing on the most promising configurations, allowing for trade-off between number/cost of TSV vs. signal path/sub-path lengths.
Below examples of 3D Stack Planning Interconnect Optimization on Selected Configurations.
GENIO Version 1.6 began beta besting in January and will be available for selected customers, full production and general availability by end of Q1 this year.
CONTACTS
Business: Michele Taliercio
michele.taliercio@monozukuri.eu
+39 335 5943100
Media: Chuck Byers
charles.byers@monozukuri.eu
+1 408 310 9244
Copyright © 2021 Monozukuri, All rights reserved
Link to Press Release
GENIOTM Co-Design EDA Tool Now Includes Parasitic Estimation and Stack Planning Functionalities
Rome – January 18, 2022
GENIO 1.6 Significantly Reduces Advanced Systems Total Design Time and Complexity
MZ Technologies today unveiled GENIO Version 1.6 that now includes Parasitic Estimation and Stack Planning functionalities to further slash total design time and reduces overall design complexity.
GENIOTM remains the only integrated-from-the-ground up chiplet-packaging Co-design EDA tool and the addition of the two new functions further increase its ability to meet 2.5D and 3D advanced packaging design challenges.
Parasitic Estimation enhances GENIO’s time-to-design superiority. This function enables early-on system analysis, based on virtual routes, prior to physical implementation. Parasitic Estimation is usually implemented after a chiplet-based system design and its system-level interconnects have optimized end-to-end 3D-aware signal assignment.
GENIOTM produces a pre-routing Parasitic Estimations report, based on Manhattan distances and coupled with RC and TSV/bump/C4/balls contributions, to enable early-on Static Timing Analysis. The key value is the ability to conduct static timing analysis during system exploration without waiting the results of the lengthy detailed physical routing process.
The Stack Planning Support helps designers automatically identify the best possible 3D stack configuration, given physical and electrical constraints. The new floor planning methodology provides a more efficient chiplet-based 3D-IC system organization, optimizing electrical performances and reducing the physical resources (TSVs) required for vertical interconnect.
Stack Planning provides a detailed comparison of multiple floor planning scenarios that allow the early comparison of multiple architecture configurations.
Floor plan configurations are tagged and compared. Connectivity Status dialog displays net lengths/statistics and can be filtered by Net Name, Net Group, path, sub-paths.
New 3D stack planning features are specifically designed to setup system initial configuration, improve exploration of all possible configurations, optimize and compare the most promising ones and finally suggest the optimal final solution.
In addition, Stack Planning improves manufacturability design efficiency by automating 3D-IC exploration focusing on the most promising configurations, allowing for trade-off between number/cost of TSV vs. signal path/sub-path lengths.
Below examples of 3D Stack Planning Interconnect Optimization on Selected Configurations.
GENIO Version 1.6 began beta besting in January and will be available for selected customers, full production and general availability by end of Q1 this year.
CONTACTS
Business: Michele Taliercio
michele.taliercio@monozukuri.eu
+39 335 5943100
Media: Chuck Byers
charles.byers@monozukuri.eu
+1 408 310 9244
Copyright © 2021 Monozukuri, All rights reserved
Link to Press Release