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How do you really feel about EDA360? As a semiconductor design professional? As an EDA vendor?
As I mentioned at the EDAC CEO panel, EDA360 gives us a new communication channel to attract investors and possibly reinvent EDA. Unfortunately, Cadence cannot do it alone. Unfortunately, the other EDA CEO's will not even say the word EDA360. So unfortunately EDA360 is a Cadence product versus an industry vision.
The next Design Automation Conference will be a key data point. Will Cadence introduce technology disruptive enough to move EDA360 forward? Strong enough to support the reinvention of EDA? Profitable enough to lift Cadence back to #1?
As an semiconductor professional, I'm confused as to what EDA360 can do for me in the near team (say 6-12 months). Not interested in "call to arms", "visions" or anything which will bear fruit more than a year from now.
I agree completely. Cadence had better have some cool products behind all of this PR. I would expect to see the first ones at DAC. If not, I will never write the EDA360 word again, believe it! You have fair warning John (Bruggeman)!
EDA360 is a joke. I saw the whole song and dance at CDNLive. It was embarrassing! I also hear about Cadence tools beating this tool and that tool bad mouthing everybody else. How about Cadence talk about solving my problems and not trying to cram VISIONS up my butt? How about Cadence walking in my shoes for a 60 hour week? Okay I'm grumpy today but see how you feel after debugging Skill scripts part of night!
I think EDA360 can be a good thing. IP integration is getting harder every node. The concept of pre integrated IP stacks is interesting. I wonder if Synopsys will do this too since they have the most IP? I think Mentor and Magma are at a disavantage without IP. If I were Synopsys I would buy more IP companies and monopolize. The other EDA360 stuff does not seem as interesting but honestly I have not read the paper. I saw EDA360 at DAC last year. They had a pretty good party!
I still do not see what this EDA360 fuss is all about ? It has been what we have been doing all the time. My company does everything from software development, hardware reference designs, system and ic design as well as test and measurement.
The EDA tools that we use for all these purposes are different, but they are different for a reason. There is no point integrating Matlab or C++ into the Cadence IC design environment, and at the same time spreadsheets are still the most flexible (and cheap) tool to use. Plus merging linux and windows environments will just result in a big catastrophe.
And as far as Cadence is concerned, they are not eager to replace the Cadence PDKs (IC design) with iPDKs as they will lose their foot in the foundry's door, so where is the "openness" they are pushing for ?
Am I missing something ? Is EDA360 just really "generalhot air" ? What exactly is it ? Can someone be more specific ?
EDA360 may have changed since then but it was described as a "vision" and not a "product road map". So yes, a little confusing. The other guy who writes about EDA360 is from Denali Steve Lisbon who has less to say with more words.
I asked our Cadence support guy about it a while back and he rolled his eyes so probably more marketing buzz than technology.
I had a read of that Q&A article and still none the wiser. It is like saying that we need to do things better ... the truth is ... we are already trying to achieve that goal, no thanks to EDA companies.
If Cadence is really serious about EDA360, they will need to completely open up their platforms. Let's start with open access tools, iPDKs, etc ...
If there is an open platform, then us designers can pick the best match of tools to our jobs. For example, I could choose any iPDKs from any foundry, a simple schematic entry tool from Linear Tech maybe, simulator from BDA, layout tool from Tanner, DRC/LVS/PEX from Mentor, EM simulator from Ansoft etc ...
Unfortunately, this will never happen as every EDA company will try to lock us into their tool chain ... including Cadence.
Can anyone in the EDA360 camp actually articulate some lower time-to-market, lower cost of ownership (end to end chip design effort) or other advantages that will make significant changes to the industry? Is it easier to integrate and test IP? Can I integrate 50 IP blocks in a day? Can I migrate my design between technologies and/or platforms easily (say, FPGA to eASIC to 65nm ASIC to 32nm ASIC)??
Mike,
At DesignCon I asked people from Cadence for something measurable with EDA360 this year compared to last year and one thing that I heard was, "Our new router is 2X faster for 28nm designs". More info in my trip report.
