After a successful debut last year DVCon India is again going to happen in Bangalore in September 10 - 11, 2015. The two days conference is a great opportunity for researchers as well as Industry Experts to present their work in front of rich audience comprising of system architects, verification experts, SoC integrators, chip designers, IP developers, VIP developers and firmware engineers.
The "Call for Paper" for DVCon 2015 is open and below are details.
Important dates:
There are two tracks in the conference. ESL track is focused on system level design, verification and prototyping. Submissions are encouraged (but not limited to) in the following areas
The DV track is focused on SoC design, verification and prototyping. Submissions are encouraged (but not limited to) in the following areas
The details of submission guidelines are available at DVCon India » » Call for Papers
The "Call for Paper" for DVCon 2015 is open and below are details.
Important dates:
- June 30: Abstract submission deadline
- July 15: Paper accept/reject notification
- August 15: Final paper + PPT/PDF due
- September 10-11 (Thur-Fri): DVCon India conference
There are two tracks in the conference. ESL track is focused on system level design, verification and prototyping. Submissions are encouraged (but not limited to) in the following areas
- Transaction-level modeling for system-level design (VP, Multi-core, Performance, etc.)
- SystemC Language Development
- Verification Techniques using SystemC-UVM and VPI/PLI, DPI Interface
- Mixed-language environments involving SystemC and SystemVerilog/UVM
- SystemC Analog/Mixed-Signal Extensions & Power Modeling
- High-level synthesis from ESL languages SystemC/C++
- System-level design techniques, flows and methodologies
- Hardware/software/embedded co-design for early development
- HW/SW Co-Simulation and SoC Architecture Exploration
- Debugging Techniques and Configuration and Control in Platform Design
The DV track is focused on SoC design, verification and prototyping. Submissions are encouraged (but not limited to) in the following areas
- Using multiple HDLs and/or HVLs in a design cycle
- Novel application of existing standard DV (Design-Verification) languages such as SystemVerilog, PSL, e, VHDL, etc.
- Latest language developments in SystemVerilog
- Advanced stimulus generation methods, reuse of stimulus across levels of verification (portable stimulus)
- System-on-Chip Verification approaches to handle complexity, performance and reusability requirements
- Adoption of UVM
- Advanced techniques/features and extensions to UVM
- Real life applications of assertions using SVA and/or PSL
- Formal and semi-formal techniques, Assertion automation/synthesis
- Verification process and resource management
- Compliance and requirements-driven verification such as DO-254 standards
- Debug automation through transaction-level debug, smart tricks to handle performance issues, faster time to debug techniques
- Low Power intent verification through standards such as UPF and related technologies
- Usage of IPXACT and SystemRDL in design flow
- AMS challenges in Verification, usage of custom extensions to UVM/SystemVerilog to handle AMS related complexities
The details of submission guidelines are available at DVCon India » » Call for Papers