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Shouldn't we be moving to a higher level of abstraction in design capture in order to support moving to tools and techniques beyond RTL?
Clocks in a design description seem like a bad idea to me, I think they should not appear until after synthesis - along with power management and other low-level hardware concepts.
I couldn't agree more. It opens up a whole can of worms. I am not a digital designer, but I seem to remember some C to RTL synthesis tools a couple of years back. Surely they must have matured ?
Another tool that I would like to see is a "visual" mixed signal schematic/block capture tool. When I was working on some digital design in the past, I had this very useful graphical tool by Expressive Systems ... which created the leaf cells and defined the interconnect between different digital and analogue blocks very well. I think it is a step up from the emacs text editor !
I think tools like Catapult-C from Mentor and similar tools are already doing that. I only have this information from the demos but you first 'program' a design in a higher level language and afterwards start to investigate clock speed, pipeline depth, area, power, etc. trade-offs. In general this way of designing is called ESL (Electronic System Level) design.
But from the title I thought you meant something like asynchronous design (also called self-timed circuits). A technique long promised to get out of clock-tree synthesis hell and clock power consumption but that never really took off because it changes the whole design flow.
Here is a (very) brief summary of how I remember the basic principle. It is based on state machines where part of the outputs are fed back into the circuit in such a way that the state machine goes to the next stage when some of the inputs are changed without using flip-flops that are driven by a clock. One of the big problems is that the circuit has to be glitch free as otherwise the state machine may wander off in an unwanted state.
