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Daniel Payne

MOS-AK Workshop Dresden 2018
Dresden, Sept. 3, 2018

The MOS-AK Compact Modeling Association, a global compact/SPICE modeling and Verilog-A standardization forum, held its 16th MOS-AK Workshop in the timeframe of ESSDERC/ESSCIRC. The event was hosted on September 3rd, 2018, by the TU Dresden in Dresden, Germany. The technical program of the event was coordinated by the MOS-AK TPC Committee. The workshop has received technical program promotion provided by ASCENT Network, Europractice, EPFL EDlab, IJHSES as well as NEEDS of

The MOS-AK workshop was opened by Wladek Grabinski, who has welcomed all the attendees. A group of 30+ international academic researchers and modeling engineers attended 10 technical compact modeling presentations covering full development chain from the nanoscaled technologies thru semiconductor devices modeling to advanced IC design support.

The workshop was chaired by Larry Nagel, OEC (USA), Suba Subramaniam, XFAB (D) and Matthias Bucher, TUC (GR). In the first morning session Wladek Grabinski gave an overview of the MOS-AK Community. Afterwards, Prof. Muhammad Mustafa Hussain from KAUST (SA) held a talk of “Physically Compliant CMOS Electronics Enabled Interactive Electronic System”. It followed a talk by Dr. Sadayuki Yoshitomi from Toshiba Memory Corp. (J) gave some insights of “RF CMOS Compact modeling technologies past and future”.
Krishna Pradeep from ST Microelectronics (D) started the second morning session with a talk entitled “Analysis and modeling of wafer level process variability in advanced FD-SOI devices using split C-V and gate current data”. Kerim Yilmaz from TH Mittelhessen (D) offered a modeling approach for “Scaling correlation between DG & GAA MOSFETs”. Dr. Laurie Calvet from University Paris-Sud (F) held a talk on “Compact Modeling for Neuromorphic Applications”. The morning session ended with “Advanced PDK and Technologies accessible through ASCENT” by Dr. Luca Perniola from CEA (F).

The afternoon session continued with four additional talks, where Dr. Farzan Jazaeri from EPFL (CH) gave a talk on “Reliability Modeling in Harsh Radiation for Space Applications”. Prof. Benjamin Iniguez from URV (SP) explained the latest results on “Low frequency noise modeling of organic and IGZO TFTs”. Dr. Mike Schwarz from NanoP (D) continued with the topic “Schottky Barrier MOSFET Device Physics for Cryogenic Applications“. The session was closed by a talk of Dr. Daniel Tomaszewski, ITE (PL), on various methodologies of “Compact Modeling for Process and Device Characterization”.

The MOS-AK speakers have shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in the dynamically evolving semiconductor industry and academic R&D. The event featured advanced technical presentations covering compact model development, implementation, deployment and all the presentations are available online for download at MOS-AK Workshop Dresden 2018.
View attachment 22315
Part of the participants of the 16th MOS-AK Workshop at ESSDERC/ESSCIRC

Afterward all the participants could follow ESSDERC Track4 "Compact modeling of devices and circuit" on Sept. 5-6, 2018
Wednesday 14:20-15:40 B4L-G Compact Modeling (3 papers)​
Chair: Wladek Grabinski, Thierry Poiroux​
Thursday 10:20-12:0 C2L-F Compact Modeling of Electron Devices (4 papers)​
Chair: Daniel Tomaszewski, Benjamin Iniguez​

The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses in Europe, USA, China and India throughout coming 2018/2019 years, including:

About MOS-AK Association:
MOS-AK, an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common information exchange system among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools including FOSS for the compact/SPICE models development, validation/implementation and distribution. For more information please visit: