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ASML reaches 'first light' milestone on first High NA EUV tool

Daniel Nenni

Daniel Nenni

Admin
Staff member
Illustration shows ASML logo

ASML logo is seen near computer motherboard in this illustration taken January 8, 2024. REUTERS/Dado Ruvic/Illustration/File Photo

AMSTERDAM, Feb 28 (Reuters) - ASML (ASML.AS), has reached "first light" on its massive new High NA EUV lithography system, the Dutch semiconductor equipment maker confirmed on Wednesday, a milestone that means the tool is functioning though not at full performance.

The head of technology development at Intel, (INTC.O), opens new tab Ann Kelleher, first mentioned the progress during a talk at the SPIE lithography conference on Tuesday in San Jose.

ASML confirmed Kelleher's remarks were accurate. Lithography systems use focused light beams to help create the tiny circuitry of computer chips. ASML's High NA EUV tools, which are the size of a double decker bus and cost more than $350 million each, are expected to help enable new generations of smaller, faster chips.
The first High NA tool in existence is at ASML's laboratory in Veldhoven, Netherlands and the second is under assembly at an Intel plant near Hillsboro, Oregon.
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Advanced chipmakers including TSMC and Samsung are expected to adopt the tool in the coming five years, with Intel saying at an event last week it intends to use the tool in production for its 14A generation of chips.

In Kelleher's talk she said that the Veldhoven machine has seen the "first light on wafer in resist," meaning the machine has been used in a test on a silicon wafer that has been treated with light-sensitive chemicals so that it is ready to receive a circuit pattern.

An ASML spokesperson said the first light milestone had been reached "very recently".

 
Daniel Nenni said:
Illustration shows ASML logo

ASML logo is seen near computer motherboard in this illustration taken January 8, 2024. REUTERS/Dado Ruvic/Illustration/File Photo

AMSTERDAM, Feb 28 (Reuters) - ASML (ASML.AS), has reached "first light" on its massive new High NA EUV lithography system, the Dutch semiconductor equipment maker confirmed on Wednesday, a milestone that means the tool is functioning though not at full performance.

The head of technology development at Intel, (INTC.O), opens new tab Ann Kelleher, first mentioned the progress during a talk at the SPIE lithography conference on Tuesday in San Jose.

ASML confirmed Kelleher's remarks were accurate. Lithography systems use focused light beams to help create the tiny circuitry of computer chips. ASML's High NA EUV tools, which are the size of a double decker bus and cost more than $350 million each, are expected to help enable new generations of smaller, faster chips.
The first High NA tool in existence is at ASML's laboratory in Veldhoven, Netherlands and the second is under assembly at an Intel plant near Hillsboro, Oregon.
Advertisement · Scroll to continue

Advanced chipmakers including TSMC and Samsung are expected to adopt the tool in the coming five years, with Intel saying at an event last week it intends to use the tool in production for its 14A generation of chips.

In Kelleher's talk she said that the Veldhoven machine has seen the "first light on wafer in resist," meaning the machine has been used in a test on a silicon wafer that has been treated with light-sensitive chemicals so that it is ready to receive a circuit pattern.

An ASML spokesperson said the first light milestone had been reached "very recently".

Click to expand...


"In Kelleher's talk she said that the Veldhoven machine has seen the "first light on wafer in resist," meaning the machine has been used in a test on a silicon wafer that has been treated with light-sensitive chemicals so that it is ready to receive a circuit pattern."

Should this type of milestone be achieved in ASML's own lab before delivery the machine to a customer site?

I'm wondering why Intel needs to get the High NA machine installed even before ASML figuring out some fundamental features and capabilities?
 
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The reduction in time by not doing things sequentially is worth the increased risk. It isn't like they could change the design anyways. This way they start learning sooner in Veldhoven and transfer the knowledge to Oregon.
 
hist78 said:
"In Kelleher's talk she said that the Veldhoven machine has seen the "first light on wafer in resist," meaning the machine has been used in a test on a silicon wafer that has been treated with light-sensitive chemicals so that it is ready to receive a circuit pattern."

Should this type of milestone be achieved in ASML's own lab before delivery the machine to a customer site? I'm wondering why Intel needs to get the High NA machine installed even before ASML figuring out some fundamental features and capabilities?
Click to expand...

In January I was told that Intel was still installing the machine so that is good progress. Hopefully ASML and Intel are working closely together on this. First to HNA is a pretty big brag so I'm not surprised Intel is working in parallel.
 
hist78 said:
"In Kelleher's talk she said that the Veldhoven machine has seen the "first light on wafer in resist," meaning the machine has been used in a test on a silicon wafer that has been treated with light-sensitive chemicals so that it is ready to receive a circuit pattern."

Should this type of milestone be achieved in ASML's own lab before delivery the machine to a customer site?

I'm wondering why Intel needs to get the High NA machine installed even before ASML figuring out some fundamental features and capabilities?
Click to expand...
The first unit in IMEC has been up and running experiments already, with ASML reporting on the results of where they saw the best value props for high-NA are at SPIE this year. Ann is talking about her development tool in her fab, and ASML just "confirmed" that this tool is now functional.

Bluestone linked this Gem earlier
 
hist78 said:
"In Kelleher's talk she said that the Veldhoven machine has seen the "first light on wafer in resist," meaning the machine has been used in a test on a silicon wafer that has been treated with light-sensitive chemicals so that it is ready to receive a circuit pattern."

Should this type of milestone be achieved in ASML's own lab before delivery the machine to a customer site?

I'm wondering why Intel needs to get the High NA machine installed even before ASML figuring out some fundamental features and capabilities?
Click to expand...
I remembered intel moved-in HNA EUV on 4th/or 5th of Jan 2024. This sounds like this tool power-up within 2 months, If having first test wafer print, it is amazing. Waiting for the next milestone of finishing acceptance tests and releasing for production, which might take a while. If the tool can be released by mid of this year, it will be definitely ahead of schedule.
 
hskuo said:
I remembered intel moved-in HNA EUV on 4th/or 5th of Jan 2024. This sounds like this tool power-up within 2 months, If having first test wafer print, it is amazing. Waiting for the next milestone of finishing acceptance tests and releasing for production, which might take a while. If the tool can be released by mid of this year, it will be definitely ahead of schedule.
Click to expand...
Wow that would be something for such an early tool and first for a customer.

Will being first really result in a materially advantage in Intels return to leadership will take years to validate.
 
nghanayem said:
The first unit in IMEC has been up and running experiments already, with ASML reporting on the results of where they saw the best value props for high-NA are at SPIE this year. Ann is talking about her development tool in her fab, and ASML just "confirmed" that this tool is now functional.
Click to expand...
This is wrong. See IMEC info https://www.imec-int.com/en/press/imec-demonstrates-readiness-high-na-euv-patterning-ecosystem

The first High-NA EUV scanner (TWINSCAN EXE:5000) has been assembled by ASML and the first wafers will be exposed soon. In the next few months, the joint imec-ASML High-NA EUV Lab will be operational, and access will be provided to the High-NA customers. The High-NA EUV lab, with the installed equipment and processes, enables an early start of High-NA EUV learning for the customers before tools are operational in their fabs. It has been imec’s role, in tight collaboration with ASML and our extended supplier network, to ensure timely availability of advanced resist materials, photomasks, metrology techniques, (anamorphic) imaging strategies, and patterning techniques. Readiness of these processes for High-NA enablement is shown in more than 25 papers presented at the 2024 SPIE Advanced Lithography & Patterning Conference.”
 
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