Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/asmls-next-chip-challenge-rollout-of-its-new-350-million-high-na-euv-machine.19594/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021370
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

ASML's next chip challenge: rollout of its new $350 million 'High NA EUV' machine

Daniel Nenni

Admin
Staff member
A High NA EUV tool is seen before the attachment of its top module as it is assembled at ASML’s headquarters in Veldhoven, Netherlands, November 14, 2023. ASML/Michel de Heer/Handout via REUTERS

A High NA EUV tool is seen before the attachment of its top module as it is assembled at ASML’s headquarters in Veldhoven, Netherlands, November 14, 2023. ASML/Michel de Heer/Handout via REUTERS© Thomson Reuters
By Toby Sterling


VELDHOVEN, Netherlands (Reuters) - Chip toolmaking giant ASML said on Friday it was gearing up production of its new $350 million "High NA EUV" machine, a device the size of a double decker bus central to its bid to keep its lead in a $125 billion market.

The machine, which went on display for the first time on Friday in the Dutch headquarters of Europe's largest tech company by market value, is aimed at Intel and other makers of the highest-end semiconductors.

ASML said it was expecting to ship "a number" of them this year, and there was still work to do on customising and installation.

"We keep engineering and developing and there's a lot of work to be done to calibrate it and make sure it fits into the manufacturing system," ASML spokesperson Monique Mols said. "There's also a steep learning curve for us and our customers."

Workers at Carl Zeiss ZMT are seen outside giant vacuum chambers where optical systems for ASML’s new High NA EUV tool are tested. ASML is rolling out its newest product line, High NA EUV lithography tools, which cost more than $350 million each and will be used by leading semiconductor manufacturers to help make new generations of smaller and better computer chips in Oberkochen, Germany, December 12, 2023. ASML/ZEISS/Handout via REUTERS


Workers at Carl Zeiss ZMT are seen outside giant vacuum chambers where optical systems for ASML’s new High NA EUV tool are tested. ASML is rolling out its newest product line, High NA EUV lithography tools, which cost more than $350 million each and will be used by leading semiconductor manufacturers to help make new generations of smaller and better computer chips in Oberkochen, Germany, December 12, 2023. ASML/ZEISS/Handout via REUTERS© Thomson Reuters
ASML is the only maker of a key technology - extreme ultraviolet (EUV) photolithography - needed to manufacture the most advanced chips.

High NA EUV is the next generation of that technology. But analysts said it was an open question how many customers are ready to switch over to the high-cost devices.

Customers could choose to wait and squeeze more out of existing tools. Koch's own calculations suggested it would only become cost effective to switch over from the older technology around 2030-2031.

ASML CEO Peter Wennink told Reuters in January analysts may be underestimating the technology.

"Everything that we're currently seeing in the discussion with our customers is that High NA is cheaper," he said in an interview.

Greet Storms, head of ASML's High NA product management, said on Friday an inflection point is coming around 2026-2027.

"This is the point clients will take it into volume production," she told reporters.

Intel has already taken delivery of one pilot device, and said it plans to start production next year, without giving details on the scale of the operation.

TSMC and Samsung have said they intend to use the tool but have not specified when.

ASML says it has taken between 10 and 20 orders to date - including pilot devices for memory specialists SK Hynix and Micron - and is building capacity to be able to deliver 20 annually by 2028.

None of them will go to China, ASML's second-largest market last year, as the United States seeks to curb exports of cutting-edge technology there and stymie Beijing's semiconductor ambitions.

Last month though, the company, considered a bellwether for the chip industry, reported a robust order book which soothed investors' concerns that limits on China would hurt its performance.

A quick take-up of the tool would boost ASML's sales and margins and could extend its dominant position in the market for lithography systems, machines that use light to help trace out patterns on silicon wafers that will eventually become the circuitry of computer chips.

It says the High NA tool will let chipmakers shrink the size of the smallest features on their chips by up to 40%, allowing density of transistors to nearly triple.

ASML competes with Nikon and Canon of Japan to make the lithography machines used to make relatively older generations of chips.

But in the late 2010s, the Dutch firm became the first and only company to market a lithography tool using EUV, or 13.5 nanometre wavelength light.

Both the original and High NA machine create EUV light by vaporizing droplets of tin with twin laser pulses 50,000 times a second.

ASML says the High NA machine's biggest change is a larger optical system consisting of irregularly shaped mirrors, made by Carl Zeiss, polished so smooth they must be kept in a vacuum. They collect and focus more light than their predecessors - High NA stands for high numerical aperture - which is what the company says leads to better resolution.

 
"Intel has already taken delivery of one pilot device, and said it plans to start production next year, without giving details on the scale of the operation." "TSMC and Samsung have said they intend to use the tool but have not specified when."

Intel is starting production next year?
 
This whole hi-NA thing strikes me as funny
VELDHOVEN, Netherlands (Reuters) - Chip toolmaking giant ASML said on Friday it was gearing up production of its new $350 million "High NA EUV" machine, a device the size of a double decker bus central to its bid to keep its lead in a $125 billion market.
Is 350M a credible number? I thought the rumor was that EUV tools were 150M per pop (granted that could be for a less capable configuration). My understanding was ASML charges for performance and even folks who are bullish on Hi-NA surely don't think it is 2.33x better than a low-NA tool? As even for cases where you get to do DP, instead of having to resort to MP, a per unit cost that high surely torpedoes the TVO, no?
High NA EUV is the next generation of that technology. But analysts said it was an open question how many customers are ready to switch over to the high-cost devices.
Obviously tool vendors will always overhype their newest best thing since sliced bread tool, but the number of hit pieces on high-NA from folks who have no clue what they are talking about is hilarious to me. The fact that a piece from our favorite dart thrower (Dylan Patel) caused enough stir with investors that ASML felt the need to write up a formal response to the non technical press is simply *chef's kiss*. Dylan's writing seems too technical for the general populace, so how he has gotten this level of sway is beyond me. You would think the people who could understand his writing would be able to kind of understand and at the very least value Fred's actually data drive arguments against the ultra fine pitch applications of Hi-NA (and regular EUV for that matter), but oh well.
Customers could choose to wait and squeeze more out of existing tools. Koch's own calculations suggested it would only become cost effective to switch over from the older technology around 2030-2031.
You heard it here first on MSN folks. Nobody is building any more fabs we will only do conversions of N7 and beyond fabs until the 2030s :p
"Intel has already taken delivery of one pilot device, and said it plans to start production next year, without giving details on the scale of the operation." "TSMC and Samsung have said they intend to use the tool but have not specified when."

Intel is starting production next year?
For what it is worth ASML did say the "cost inflection point would be in the 2026-2027 time frame". Time will tell, and maybe the public portion of IFS direct connect will elaborate further when they talk about 5N4Y and beyond? Could also be in reference to this slide where intel is talking about de-risking Hi-NA on 18A in a manner that seems reminiscent of N7+?
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This whole hi-NA thing strikes me as funny

Is 350M a credible number? I thought the rumor was that EUV tools were 150M per pop (granted that could be for a less capable configuration). My understanding was ASML charges for performance and even folks who are bullish on Hi-NA surely don't think it is 2.33x better than a low-NA tool? As even for cases where you get to do DP, instead of having to resort to MP, a per unit cost that high surely torpedoes the TVO, no?

Obviously tool vendors will always overhype their newest best thing since sliced bread tool, but the number of hit pieces on high-NA from folks who have no clue what they are talking about is hilarious to me. The fact that a piece from our favorite dart thrower (Dylan Patel) caused enough stir with investors that ASML felt the need to write up a formal response to the non technical press is simply *chief's kiss*. Dylan's writing seems too technical for the general populace, so how he has gotten this level of sway is beyond me. You would think the people who could understand his writing would be able to kind of understand and at the very least value Fred's actually data drive arguments against the ultra fine pitch applications of Hi-NA (and regular EUV for that matter), but oh well.

You heard it here first on MSN folks. Nobody is building any more fabs we will only do conversions of N7 and beyond fabs until the 2030s :p

For what it is worth ASML did say the "cost inflection point would be in the 2026-2027 time frame". Time will tell, and maybe the public portion of IFS direct connect will elaborate further when they talk about 5N4Y and beyond? Could also be in reference to this slide where intel is talking about de-risking Hi-NA on 18A in a manner that seems reminiscent of N7+?
View attachment 1661

Intel says development with 18A and production with Intel Next (14A or 12A) so "High-NA EUV production next year" is incorrect. And they only have one machine for crying out loud. Not much production with one machine for R&D and none for production. :ROFLMAO:
 
Intel says development with 18A and production with Intel Next (14A or 12A) so "High-NA EUV production next year" is incorrect. And they only have one machine for crying out loud. Not much production with one machine for R&D and none for production. :ROFLMAO:
When A touts to beat or lead B in 4-5 years, usually A will create a lot of stories until the last year of the fifth year if A eventually can not achieve that goal. It happened several times in the past. This is the fifth year of intel 5N4Y. I am waiting for more stories to see intel's success in 2024.
 
High-NA needs supporting technology, such as much higher power source (may not be Sn plasma type), a pellicle that can withstand that higher power and intensity, and more absorptive metal-containing resist, all of which do not have established supply yet. For this reason, Intel can't prove anything for a while.
 
When A touts to beat or lead B in 4-5 years, usually A will create a lot of stories until the last year of the fifth year if A eventually can not achieve that goal. It happened several times in the past.
TBF this is ASML chest beating about how “awesome their new tool is”, not intel. If ASML wants to call intel doing a pilot line “in production”, I guess they aren’t technically wrong even if it is disingenuous. But maybe I am misunderstanding your point. Maybe you mean that the foundry customers, faraday, Erickson gen 2 stuff, and this Hi-NA business is indicative of failure? But if that is the case what do signs of success look like?
This is the fifth year of intel 5N4Y. I am waiting for more stories to see intel's success in 2024.
I hate to be “that guy” but it is currently year 2.5ish. Intel accelerated was in like Aug/Sept 2021, so intel has until that timeframe in 2025 to launch 18A something.
 
Lower throughput (from higher dose) increases the cost. DUV quad patterning looks suddenly quite cheap.
The cost is per layer, but not the cost of *the same* layer. Even with clever breakdown of patterns into separate elements and overlaid cuts 193i is not making the fine details that EUV LE-2 can make, and probably HNA LE 30mJ.

It is very unlikely they will run as low as 30mJ dose, though, if they want those fine details. As you have been saying, the stochastics will be terrible. If you want to improve resolution by 40% your stochastics must improve by 100%. All while your resist chemistry struggles to catch photons and the resist gets thinner. I expect the real world will be more like 50mJ minimum on the patterns that HNA is needed for.

But as long as the leading edge chips have the higher margins, the fabs will have reason to make it work for at least a few of the most critical layers.
 
When would ASML rollout machine worth a billion
I would say impossible now but not never. It could be affordable for Altman's 7 trillion manufacturing plan.
The wafer size might not be limited to 12" wafer and could be extended to 18" 24" or even 30" size.
It could happen in Mars and co-work with Elon Musk. Go for Human being.
 
TBF this is ASML chest beating about how “awesome their new tool is”, not intel. If ASML wants to call intel doing a pilot line “in production”, I guess they aren’t technically wrong even if it is disingenuous. But maybe I am misunderstanding your point. Maybe you mean that the foundry customers, faraday, Erickson gen 2 stuff, and this Hi-NA business is indicative of failure? But if that is the case what do signs of success look like?

I hate to be “that guy” but it is currently year 2.5ish. Intel accelerated was in like Aug/Sept 2021, so intel has until that timeframe in 2025 to launch 18A something.
If I was ASML, invested billion dollars in EUV/Hi NA EUV RD and manufacturing, I would always proudly promote "how awesome my new baby is" and persuade my customers to adopt it as soon as possible and to get return. It happened in EUV history and seems to be repeated in Hi NA EUV. If my memory is correct, intel was leading company to pursue the new technique (EUVL), Samsung followed and TSMC would be slow and sought alternative in parallel. Now, intel needs story in catching up technology leadership, then Hi-NA EUV to HVM will be critical in this 5N4Y. I even heard the rumor said his ahead of schedule in ribbonfet was due to getting the first Hi-NA EUV tools.
I would say Faraday, Ericcson, UMC are only the small and few pieces in a big strategy plot of IFS and which is just starting. I am waiting the curtain up on the stage and the show starts to play.
 
The cost is per layer, but not the cost of *the same* layer. Even with clever breakdown of patterns into separate elements and overlaid cuts 193i is not making the fine details that EUV LE-2 can make, and probably HNA LE 30mJ.
If we look at the same specific pattern, like 30 nm pitch lines, 193i LE-4 (LE-3 enough) is still cheaper than EUV LE-2, which is necessary due to stochastics. SALELE also requires EUV LE-2 cuts, which would still be costlier than 193i LE4.
It is very unlikely they will run as low as 30mJ dose, though, if they want those fine details. As you have been saying, the stochastics will be terrible. If you want to improve resolution by 40% your stochastics must improve by 100%. All while your resist chemistry struggles to catch photons and the resist gets thinner. I expect the real world will be more like 50mJ minimum on the patterns that HNA is needed for.

But as long as the leading edge chips have the higher margins, the fabs will have reason to make it work for at least a few of the most critical layers.
It's not just the stochastics though, there's also electron blur, regardless of NA. This has never been truly pinned down cleanly, especially coming from outside the resist.
 
Yeah but they are not buying HNA or even EUV to do boring 30nm lines that 193i can do nicely with pitch splitting from a single exposure. They buy EUV to do complex cuts, vias, and maybe even some 2D patterns in metals (though probably not below 5nm).

Yes I agree the electron blur is going to be a serious issue when they imagine they will have 18nm pitch. It is less of an issue with low voltage ebeam where the incoming electrons have momentum, than with EUV where the electrons go every direction equally. But very little work has been done on it, and it is pointless going back in the literature since so many experiments failed to log basic characteristics like resist conductivity that matter now, but where not caring or being curious has become the norm.
 
Not entirely related to dose, but an interesting paper from IBM talking about critical applications for low and high NA EUV for HNS FET.
 
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