You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!
Thanks Andy!
I checked RedHawk document and it says that, the small resistance from "Clamp" to "core instance" is to prevent CDM failures.
If the "RESISTANCE" is big, then, the CDM current flows from substrate (Nwell or Pwell) through S(source) or D (drain) of core FET to "Clamp" will cause a...
HI everyone!
Could anyone please help to explain why should we care about the effective resistance from a "core clamp cell" to "core instance?
I'm usually measure "pin to pin", "pin to clamp" "clamp to clamp" resistance.
Thanks!