Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/why-should-we-care-the-effective-resistance-from-an-esd-clamp-cell-to-core-instance-clamp2inst.13189/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/JobRunner] => 2000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000670
            [ThemeHouse/XPress] => 1010394
            [XF] => 2020170
            [XFI] => 1040070
        )

    [wordpress] => /var/www/html
)

Why should we care the effective resistance from an ESD clamp cell to core instance? (CLAMP2INST)

vule

New member
HI everyone!

Could anyone please help to explain why should we care about the effective resistance from a "core clamp cell" to "core instance?
I'm usually measure "pin to pin", "pin to clamp" "clamp to clamp" resistance.

Thanks!
 
Last edited:

andyjackcao

New member
Hi ,
The core instance is weak usually, especailly at the sub-mircon process. The mos-gate is hardly suffer from ESD, if gate is exposed surge. if core instance can look ESD pulse without resitance, then there maybe dangerous
 

vule

New member
Hi ,
The core instance is weak usually, especailly at the sub-mircon process. The mos-gate is hardly suffer from ESD, if gate is exposed surge. if core instance can look ESD pulse without resitance, then there maybe dangerous
Thanks Andy!

I checked RedHawk document and it says that, the small resistance from "Clamp" to "core instance" is to prevent CDM failures.
If the "RESISTANCE" is big, then, the CDM current flows from substrate (Nwell or Pwell) through S(source) or D (drain) of core FET to "Clamp" will cause a big drop voltage. This big voltage at S (or D) can cause damage the core FET.
 
Top