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Hello Francesco,
thanks for the book, really interesting, I am currently going through it and already a couple of questions popped up:
Chapter 2.2.2 Active region formation
When I understood it correctly, the book describes two different approaches to forming the different regions on the...
Ok, understood. So the etching does not remove the Silicon but only the oxide layer above.
The n doping in this specific area (which at the end is the drain and source area) come from ion implantation.
In the infiniin video I posted they were talking about polysilicon......Is this the...
I also found another video from Infineon:
The final result is obviously the same but am I correct in my thinking, that this is a different process flow in terms of what process comes when compared to my PDF file?
Hello folks,
I am currently diving deeper into the front-end of semiconductor processing and checking multiple sources to learn how it works. I came across multiple videos on YouTube and want to check with you guys if my understanding is correct. I attach a small PDF presentation that I quickly...
Dear Peers,
another question that popped up from my side:
What kind of differentiations are done in fabs? Depending on the application the chip goes in there are some process steps that are present at some but not present at other (e.g. backside metal for IGBT but not for MEMS or sensors...
Dear Peers,
I am currently investigating the semiconductor back-end processing market a bit more in detail. But first things first, let me quickly define "back-end" since different people have different understandings about it. When I talk about semiconductor back-end processing I mean the...
Dear Semicon-enthusiasts,
I am currently asking myself how the European Chips Act will affect the wafer size trend within Europe. As we all know, Europe is especially strong in power devices and sensors, both applications mainly run on 8" wafers. Increasing wafer size of course would increase...
Dear Semicon colleagues,
does anyhow have a reliable and up-to date source of wafer sizes of the European semiconductor market? I am especially interested in the split between 8" and 12" Si-Wafers
- What is the total numbers of 8" and 12" wafers processed in the EU
- What is the split between...
