ramesh_dasara

(... continued ...)
If it is an analogue design, then how are the schematics entered, netlisted and simulated and how were the devices generated on the layout ? This depends on the IC tool + PDK/TDK/iPDK you use.

TSMC now produces iPDKs (I think) for their newer processes (130nm and below ...). Then it is up to the tool vendors (Cadence, Mentor, Magma, etc ...) to put the "hooks" in their tools to uses these iPDKs.

Mentor have a history of being "overworked" as they are not able to put these "hooks" for all the processes that are available on TSMC (and other foundries). If you are lucky, someone else would have already requested for it and you are ready to use the iPDKs, else it will have to go to Mentor support which takes anything from 2 weeks to 10 weeks to "build" depending on how big your account is with Mentor.

That is all I can offer right now ... if you need something more specific, you can hire me as your consultant and I can offer better advice/details !

Regards,
Harpoon.

Hi Ramesh,

Sorry for the long silence ... I was in the middle of a tapeout the past few weeks (with TSMC) !

Let me correct myself.

If you are able to produce a GDSII (from whatever tool) and get a clean DRC using Calibre with TSMC's calibre rule decks (no modification needed, just need to put in the right options regarding metal stack, etc ...), then you can tape out on TSMC.

The question then is how you produced that GDSII.

(... please read next post ...)