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Recent content by Daniel Payne

  1. Daniel Payne

    Aldec at SC19: Showcasing Multi-FPGA Partitioning Software for Multi-FPGA-based Algorithm Accelerators

    November 18-21, Denver Colorado Booth #228, Aldec Inc. We will showcase the recently introduced automatic FPGA partitioning feature of our popular HES-DVM™ tool, our fully automated and scalable hybrid verification environment for large SoC designs. Manual partitioning of designs with...
  2. Daniel Payne

    With proFPGA quad Intel® Stratix® 10 GX 10M System, PRO DESIGN Reaches a new Level in FPGA-based Prototyping

    Munich, 18 November 2019 - PRO DESIGN, leading supplier of high-speed ASIC and SoC verification platforms, today announced the launch of its innovative high-capacity proFPGA quad Stratix® 10 GX 10M system. It is the next generation of its successful, modular, scalable and most compact...
  3. Daniel Payne

    TSMC Files Complaints Against GlobalFoundries in U.S., Germany and Singapore for Infringement of 25 Patents!

    The lawyers are going to get rich, and the two foundries will settle out of court, both claiming victory in the next 12 months or so. Such a common corporate tactic in high-tech to file countering complaints on patent violations.
  4. Daniel Payne

    New Apple iPhones (meh)

    When I read the benchmark comparison between an iMac 2019 vs iPhone 11, it shows the Intel-based iMac with higher scores:
  5. Daniel Payne

    New Apple iPhones (meh)

    I was also impressed with the 8.5 billion transistors of the A13 chip on the 7nm+ process, along with improved battery life. So glad to have invested in AAPL stock a few years back. Also amazed at the growth of services at Apple, but their streaming service is clearly not ready to compete with...
  6. Daniel Payne

    VLSI Design Methodology Development Webinar Replay and Follow up Q&A!

    Tom, very comprehensive topics in your book with 700+ pages. I look forward to added content on topics like: packaging, 2.5D, 3D chips, chiplets, IBIS modeling.
  7. Daniel Payne

    IP Security Assurance Standard - White paper

    Authors Brent Sherman, Intel Corporation Mike Borza, Synopsys James Pangburn, Cadence Design Systems, Inc. Ambar Sarkar, NVIDIA Corporation Wen Chen, NXP Semiconductors Anders Nordstrom, Synopsys Kathy Herring Hayashi, Qualcomm Michael Munsey, Methodics John Hallman, OneSpin Solutions Alric...
  8. Daniel Payne

    Is EETimes Dead? Again?

    The first end was Richard Goering exiting EE Times, because he covered so much of the EDA industry for so long.
  9. Daniel Payne

    Is EETimes Dead? Again?

    So sad, but kind of predictable. EE Times was my go-to weekly reading starting back in 1978.
  10. Daniel Payne

    1.2 Trillion transistor chip? Yes - Cerebras

    OK, just read the article at https://www.anandtech.com/show/14758/hot-chips-31-live-blogs-cerebras-wafer-scale-deep-learning, where it shows die mounted to a substrate, now that makes sense.
  11. Daniel Payne

    1.2 Trillion transistor chip? Yes - Cerebras

    Yes, chiplets is an approach, however this is never mentioned in any of the public Cerebras information. Do you have some private insight?
  12. Daniel Payne

    1.2 Trillion transistor chip? Yes - Cerebras

    Cerebras used a TSMC 16nm process, but somehow they worked to increase the reticle size beyond 32mm x 26mm to fill an entire wafer, or it's likely that they did multiple exposures at the maximum reticle size. I really haven't heard of other fabs doing full-wafer chips because the yield...
  13. Daniel Payne

    1.2 Trillion transistor chip? Yes - Cerebras

    Arthur, we have to wait for Cerebras to disclose more details at the Hot Chips conference, so this is quite the accomplishment to actually get yield on a 16nm Wafer Scale Integration (WSI) project. At Intel there was research into WSI going back to 1978, but the equations predicted that you...
  14. Daniel Payne

    1.2 Trillion transistor chip? Yes - Cerebras

    Yeah, the largest wafer-scale chip on the planet award goes to Cerebras at 1.2 trillion transistors. Aimed at speeding up ML operations, this is outrageously interesting. In theory as a die size increases the yield should approach zero, so how did Cerebras and TSMC team up to create this mammoth...
  15. Daniel Payne

    ISQED'20 - Call for Contributions, deadline September 14

    21st ISQED - March 25-26, 2020 - Santa Clara Convention Center, California About the Conference A pioneer and leading interdisciplinary conference, the 21st International Symposium on Quality Electronic Design (ISQED2020) accepts and promotes original and unpublished papers related to the topics...
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