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Conquer SI/PI Challenges and Reduce Time to Signoff for PCIe 6.0

Online

Overview The Peripheral Component Interconnect Express (PCIe®) high-speed interface has become the standard for computer expansion cards due to its high bandwidth combined with manageable component costs. However, the latest PCIe 6.0 release raises new challenges for design engineers, as the popular interface standard moves to pulse-amplitude modulation-4 (PAM-4) signaling for the first time. This …

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Technical Education Webinar Series: Three Issues Every EE Needs to Overcome to Sign Off on High-Speed PCB Designs

Online

Sponsored by: Cadence Presented by: Nitin Bhagwath, Director of Product Management Event Duration: 60 minutes Abstract: Signal integrity/power integrity (SI/PI) are top priorities for engineers designing today’s high-speed, high-density circuit boards. Faster signoff …

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Cadence TechTalk: Design Robust IC Packages Faster Using In-Design SI/PI Analysis

Online

IC package design teams and characterization teams have had a “throw-it-over-the-wall” relationship for decades, which often delays design releases by months. However, as signal integrity (SI) and power integrity (PI) challenges evolve with multi-die heterogeneous integration, the need to perform SI/PI analysis as part of the design flow has become a requirement to meet compressed …

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