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Webinar Details Creating Assertions for SV Real-Number Modeling Date: Wednesday, June 17, 2020 Time: 09:00 EDT / 14:00 BST / 15:00 CEST / 18:30 IST Questions about this event? Send email to: eur_training@cadence.com Device assertions and checks have been used in analog simulation for years. These checks, however, are more focused on device characteristics such as voltage, current, …
Date: Wednesday, June 7, 2023 Time: 11:00 am PDT | 2:00 pm ET | 8:00 pm CEST Xcelium mixed-signal simulation enables teams to achieve digital simulation speeds of analog models and opens mixed-signal designs to advanced verification techniques typically applied within standard verification flows. Built on a SystemVerilog Real Number Modeling (RNM) foundation, Xcelium automates …
