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WEBINAR: CREATING ASSERTIONS FOR SV REAL-NUMBER MODELING

June 17 @ 9:00 AM - 5:00 PM

Webinar Details

Creating Assertions for SV Real-Number Modeling
Date: Wednesday, June 17, 2020
Time: 09:00 EDT / 14:00 BST / 15:00 CEST / 18:30 IST

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Send email to: eur_training@cadence.com

Device assertions and checks have been used in analog simulation for years. These checks, however, are more focused on device characteristics such as voltage, current, impedance, and timing rather than functionality.

The SystemVerilog language supports assertions (SVA) for functional verification. By extending the MS simulation tools to support the binding of SVA, the assertions created for checking the functionality of SV RNM behavioral models can be re-used for checking the Spice circuit model functionality.

Join Cadence Training and Solutions Director Tim Pylant, for our free, one-hour live webinar “Creating Assertions for SV Real-Number Modeling”. In this webinar, we’ll outline the use of SVA to create MS assertions and show how they can be re-used from behavioral to circuit-level verification. We’ll also include an intro to the SVA language and show numerous examples of how to create assertions for common analog blocks.

Date and Time

Wednesday, June 17, 09:00 EDT / 14:00 BST / 15:00 CEST / 18:30 IST

Agenda

  • What is an assertion
  • Digital assertion
  • Analog assertion
  • How to access analog values
  • Examples of analog/MS assertions
  • Assertion reuse from RNM to Spice
  • Q&A session