Learn how innovative analog IP can help analog design engineers. Agile Analog is transforming the analog IP industry, with Composa, our configurable, multi-process technology that automatically generates analog IP. We …
Hardware security is essential for high-performance computing (HPC), AI, and Edge IoT applications when designing SoCs in advanced process nodes. These designs include Gigabits of SRAM and require storing >16Kb …
A worldwide connected Event !! D&R IP-SoC Silicon Valley 2024 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. IP-SoC …
(Work email required for verified registration) During a project, subsystem and full-chip integration plays a crucial role. Integration can be particularly challenging on large SoCs with distributed teams due to complexity of the integration process, multi-site infrastructure issues, as well as the need to collaborate across multiple time zones. Often, integrators must integrate design blocks …
Continue reading "Webinar: Automating the Integration Workflow with IP Centric Design"
Synopsys' SLM PVT Monitor (process detector, voltage monitor, temperature sensor) IP can collect voltage, temperature, and process parameters from different blocks within the IC in real time. These data can be analyzed and used to take meaningful action to optimize the performance of the chip at any stage of silicon lifecycle. This webinar focuses on …
Continue reading "Webinar: Reimagining Synopsys SLM PVT Monitoring IP for Advanced Node GAA Process"
The GSA European Executive Forum is our flagship event in Europe which, over two days, always attracts the very top speakers and attendees: 300 senior decision makers, the majority VP …
