Overview As designs grow in complexity, rigorous formal verification is essential to meet aggressive requirements for power, performance, area, and time to market. Equivalence checking, static verification, automated ECO, and …
Continue reading "Webinar: Conformal 2020 Updates to Improve Productivity and Silicon Success"
Synopsys Webinar | Tuesday, August 16, 2022 | 8 a.m. Pacific To achieve maximal quality of results (QoR) in synthesis, it requires leveraging retiming, multibit banking, and advanced datapath optimizations, which are part of the Synopsys Fusion Compiler™ implementation solution. However, during the late-stage functional ECO (engineering change order) phase, the automated ECO tool needs …
Continue reading "Webinar: Fast and Accurate Functional ECOs with Synopsys Formality ECO"
Wednesday, July 26, 2023 | 10:00 a.m. - 11:00 a.m. PDT RTL engineering change order (ECO) is vital to ensuring proper functionality of integrated circuits (ICs). Retiming and auto ungrouping optimize RTL implementation and enhance PPA. However, aggressive optimizations in CPU RTL designs present challenges due to increased design complexity and potential mapping issues. Synopsys Formality …
