We’re supporting a community where more than millions of people learn, share, and work together to build a chip. At VSD, where we always promote “open source,” we’re promoting about a proven method of collaborating to create technology. The freedom to see the design, to learn from it, to ask questions and offer improvements: This is the open source way.
Good news is – Anyone from any part of the world at any time-zones can join. It is open 24hrs between 27th May to 31st May. So, you can enter and exit whenever you are comfortable
Workshop Day wise Content :
Day 1 : Introduction to RISC-V ISA and GNU compiler toolchain
Introduction to RISC-V basic keywords
Labwork for RISC-V software toolchain
Integer number representation
Signed and unsigned arithmetic operations
Day 2: Introduction to ABI and basic verification flow
Application Binary interface (ABI)
Lab work using ABI function calls
Basic verification flow using iverilog
Day 3: Digital Logic with TL-Verilog and Makerchip
Combinational logic in TL-Verilog using Makerchip
Sequential and pipelined logic
Validity
Hierarchy
Day 4: Basic RISC-V CPU micro-architecture
Microarchitecture and testbench for a simple RISC-V CPU
Fetch, decode, and execute logic
RISC-V control logic
Day 5: Complete Pipelined RISC-V CPU micro-architecture/store
Pipelining the CPU
Load and store instructions and memory
Completing the RISC-V CPU
Wrap-up and future opportunities
Welcome to the two (2) day, 13th Annual Hybrid Riscure workshop on September 3 & 4th 2020. The event is will focus on topics relevant to embedded security. The delivery of the event will be webcast live to the public via registered attendees only and will have a private by invite only offline workshop (max …
Continue reading "Riscure Hybrid Workshop 2020 – Embedded Security via Webcasting & Offline"
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