The Evolution of the Extension Implant Part I

The 3D character of FinFET transistor structures pose a range of unique fabrication problems that can make it challenging to get these devices to yield. This is especially true for the all-important Extension implant that is put in place just prior to the nitride spacer formation.

The Extension implant is a central component of any transistor because the physical distance between the two elements of this high-dose implant defines the speed of the transistor. In planar transistors the Extension implant is self-aligned to the edges of the gate electrode and is the chief reason why great effort has been made in the past to minimize the Length (Lg) of the gate electrode, and in so doing, improve transistor performance.

In planar devices the Extension implant in realized by implanting dopant at a angle of 90 degrees to the silicon surface on either side of the gate electrode (refer to figure #1).

However, since the channel in a FinFET device is perpendicular to the silicon surface, this methodology is not an option. Instead, an angled implant is employed that implants the top and both sides of the fin, usually at a steep angle as illustrated in figure #2.

The issue with implanting the Extension at such a steep angle is that a large percentage of the dopant is not retained on the fin, but is instead ricocheted off. The relationship between the Extension implant angle and dopant retained on the sidewall is illustrated in figure #3. As this figure indicates, the steeper the implant angle, the less dopant is retained on the fin sidewalls.

Figure #3

Unfortunately, the height of the photoresist used to shield the PMOS devices during the NMOS Extension implant (and vice-versa) dictates that a steep double implant angle be used at an angle of + and -20 degrees. Figure #2 as illustrates one of these two implants.

This problem was mitigated in the first iteration of the FinFET architecture by the fact that the fins were sloped. This increased the incident angle of the implant and allowed more dopant to retained on the fin sidewalls. However, at the 14nm and 10nm nodes the fins were tall and vertical and the mitigating effect of sloped fins was absent (refer to figure #4).

The solution to this problem was to replace the tall photoresist used to separate the NMOS Extension implant and the PMOS Extension implant with a short hard mask that would permit a greater implant angle, and in so doing, allow a greater percentage of the dopant to remain on the fin sidewalls. Figure # 5 illustrates this approach to the problem. By employing a short hard mask material to shield the PMOS devices during the NMOS Extension implant (and vice versa), an implant angle of as much as +/-30 degrees can be used, and the majority of the dopant in the Extension implant is retained on the fin sidewalls ensuring a high performance device.

Figure #5

Of course the use of a hard mask in lieu of photoresist will only be advantageous in very dense regions where there would normally be numerous, tall photoresist lines. Since this is the most common situation on sub 14nm devices, this technique can be very useful.

However ultimately, the primary limiting factor in realizing the Extension implant into the fin is fin-to-fin shadowing. This is an increasing problem with the tall, closely spaced fins that are present at the 10nm node and below.

For more information on this topic and for detailed information on the entire process flows for the 10/7/5nm nodes attend the course “Advanced CMOS Technology 2019” to be held on May 22, 23, 24 in Milpitas California.