WP_Term Object
(
    [term_id] => 159
    [name] => Mentor, a Siemens Business
    [slug] => mentor-graphics
    [term_group] => 0
    [term_taxonomy_id] => 159
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 499
    [filter] => raw
    [cat_ID] => 159
    [category_count] => 499
    [category_description] => 
    [cat_name] => Mentor, a Siemens Business
    [category_nicename] => mentor-graphics
    [category_parent] => 157
    [is_post] => 1
)

SPIE 2018 Mentor Graphics Scott Jones and SemiWiki

SPIE 2018 Mentor Graphics Scott Jones and SemiWiki
by Daniel Nenni on 02-21-2018 at 7:00 am

Next week is SPIE, the leading lithography networking event here in Silicon Valley. Scott Jones is not only attending but also presenting at the 15th Annual LithoVision on Sunday. I will be at SPIE as well so if you want to meet up let us know. We will publish a blog on Scott’s presentation the morning of for those who cannot attend. Walking around SPIE with Scott is like walking with me at DAC, everybody knows him and wants a word or two. For the past 10 years EUV has always been a hot topic and this year will be no different since we are actually getting close to production quality EUV, absolutely.

21191-lithovision-2018.jpg

The evolving semiconductor technology landscape and what it means for lithography Scotten W. Jones, IC Knowledge LLC
The semiconductor industry is approaching fundamental physical limits on traditional scaling. This has led to major changes in devices architectures with more changes on the horizon. 2D NAND, long the driver of leading edge lithography is transitioning to 3D NAND. In 3D NAND lithography linewidths are relaxed and scaling is accomplished by adding layers. In the leading-edge logic space, planar transistors have given way to FinFETs with stacked horizontal nanosheets on the horizon. Longer term complimentary FETs with stacks of n and p nanosheets may also lead to relaxed linewidths and scaling by adding layers. In the DRAM space a fundamental tradeoff between capacitor k values and leakage has slowed scaling with no long-term solution currently available.

In this paper I will discuss the technology transitions in each of these three-key application areas and the impact on the number of lithography layers and types of exposures required.

21191-lithovision-2018.jpg

While Scott attends sessions I will be hanging out with the Mentor experts (booth #222) who are featured throughout the conference. Mentor Graphics, a Siemens Business, of course are EDA lithography royalty and will be showcasing EUV readiness and a new OPC approach for handling memory applications & flows. Papers relevant to those focus areas are listed below and here is the Mentor at SPIE landing page:

EUV Readiness

  • SRAF requirements, relevance, and impact on EUV lithography for next-generation beyond 7nm node
  • Model-based hyper-NA anamorphic EUV OPC
  • Impact of aberrations in EUV lithography: metal to via edge placement control

New OPC approach for handling Memory applications & flows

  • Model-based cell-array OPC for productivity improvement in memory fabrication
  • Model-assisted template extraction application to contact hole patterns in high end flash memory device fabrication

ALL CONFERENCE SESSIONS AND TIMES
SRAF requirements, relevance, and impact on EUV lithography for next-generation beyond 7nm node
Tuesday, February 26 | 1:30pm

Model-based hyper-NA anamorphic EUV OPC
Tuesday, February 26 | 2:10pm

Impact of aberrations in EUV lithography: metal to via edge placement control
Tuesday, February 26 | 2:30pm

Constraint approaches for some inverse lithography problems with pixel-based mask
Wednesday, February 28 | 9:10am

Model-based cell-array OPC for productivity improvement in memory fabrication
Wednesday, February 28 | 10:30am

Model-assisted template extraction application to contact hole patterns in high-end flash memory device fabrication
Wednesday, February 28 | 11:10am

A model-based approach for the scattering-bar printing avoidance
Wednesday, February 28 | 2:30pm

A novel processing platform for post tape out flows
Wednesday, February 28 | 2:50pm
Combinational optical rule check on hotspot detection
Thursday, March 1 | 11:30am

Integrated manufacturing flow for selective-etching SADP/SAQP
Thursday, March 1 | 2:20pm

Comparison between traditional SADP/SAQP and selective-etching SADP/SAQP
Thursday, March 1 | 2:45pm

POSTER SESSIONS
Tuesday, February 27 | 5:30-7:30pm

A novel method to fast fix the post OPC weak-points through Calibre eqDRC application

Exploring EUV and SAQP pattering schemes at 5nm technology node

Ultimate patterning limits for EUV at 5nm node and beyond

Inverse lithography recipe optimization using genetic algorithm

Cross-MEEF assisted SRAF print avoidance approach

A weak pattern random creation method for lithography process tuning

A smart way to extract repeated structures of a layout

Using pattern-based layout comparison for a quick analysis of design changes

An efficient way of layout processing based on Calibre DRC and pattern matching for defects inspection application

Leverage Calibre pattern matching to address SRAM verification challenges at advanced nodes

EXHIBIT FLOOR
Visit Mentor experts in booth 222 to learn about our best-in-class technology, comprehensive solutions, development and production support, and continuous innovation. The challenges of developing advanced lithography flows require a strong partner. With a complete design-to-manufacturing platform for Immersion Lithography, EUV and DSA, Mentor, a Siemens Business, is the ideal partner for semiconductor manufacturing success.

More aboutMentor Graphics on SemiWiki