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Webinar: Bottlenecks be Gone – Automated Performance Verification with Synopsys

Webinar: Bottlenecks be Gone – Automated Performance Verification with Synopsys
by Bernard Murphy on 02-14-2018 at 10:00 pm

Performance verification is among the most challenging of objectives in any SoC verification plan. It’s difficult to start effectively until quite late in the development cycle, at which point you don’t have a lot of time left to develop extensive performance-oriented testbenches. So many teams adapt functional tests to this purpose, typically a less than ideal way to truly stress performance. Even then they must comb through log and other files to extract latencies, bandwidths and other performance-related metrics, then compare these with targets.

Vaishnav Gorur, product marketing manager in the verification group at Synopsys, told me this has been a common concern he has heard from multiple verification teams and architects. This encouraged Synopsys to develop more automation around performance testing in their just-released VC VIP AutoPerformance and Verdi Performance Analyzer products. This tool automates the construction of traffic stimulus, orchestrating runtime traffic, visualizing and analyzing metrics, automating checking (did I meet targets) and diagnostic traceback (show me the packets that led to this problem).

From what I can see, there are four main components to a performance verification solution in this flow solution:
• VC AutoTestbench for building the testbench
• VIP for Arm® AMBA® protocol
• VC VIP AutoPerformance automates building the performance test from a test
• Extensive support within Verdi for performance-related metrics: latencies, bandwidths, counts, user metrics, all with user-definable thresholds, protocol-aware transaction tracking, linkages between violations and transactions, linkages to signals, memory activity/value tracking, cache operation/history tracking, you get the idea.

Synopsys has been making a big push to simplify and accelerate SoC verification. I recently introduced their webinar on automating building the SoC testbench, reducing time from a standing start to “lights-on” from days/weeks to hours. This webinar provides and overview on the solutions they are releasing targeting this objective.

You can register HERE for this webinar on February 21st at 10am PST

Abstract
Performance is a critical source of competitive advantage for modern SoCs, and performance targets need to be verified on top of functionality. SoCs can be configured in a multitude of ways with different IP and interconnect topologies, number of masters and slaves, bus widths, packet sizes, clock speeds, etc., and performance verification can quickly get overwhelming. Further, given SoC performance verification is often done towards the end of the project cycle, there is a pressing need for push-button performance verification, analysis and debug.

In this Synopsys webinar, we will outline an automated flow to perform end-to-end performance verification using Synopsys VC VIP AutoPerformance, Verdi Performance Analyzer and Verdi Protocol Analyzer. We will also include a demo of this flow using a real-world design and Synopsys VIP for Arm® AMBA® protocol.

Specifically, you will learn:
• How to quickly create a test profile for VC VIP AutoPerformance to auto-generate stimulus for performance testing
• How to easily preset thresholds for key metrics such as latency, bandwidth etc. to auto-detect performance bottlenecks
• How to analyze and seamlessly debug performance issues right down to the violating transaction

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Vaishnav Gorur
Product Marketing Manager
Verification Group, Synopsys

Vaishnav Gorur is currently Staff Product Marketing Manager for Debug & SoC Verification Automation products in the Verification Group at Synopsys. He has over 12 years of experience in the semiconductor and EDA industry, with roles spanning IC Design, field applications, technical sales and marketing. Prior to joining Synopsys, Vaishnav worked at Silicon Graphics, MIPS Technologies and Real Intent. He has a Masters degree in Computer Engineering from University of Wisconsin, Madison and an M.B.A. from University of California, Berkeley.

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Satyapriya Acharya
Senior Manager – Applications Engineering
Verification Group, Synopsys

Satyapriya Acharya is a Senior AE Manager at Synopsys, where he manages the use of Synopsys Verification IP for ARM AMBA protocols with several key customers. He has been involved in the development, verification, and deployment of Synopsys Verification IP for the AMBA 3, AMBA 4 and AMBA 5 specifications. He has over 15 years of experience in design and verification.