Cadence, Synopsys, and Mentor on FinFETs

In my opinion, FinFETs will be the most significant piece of technology we, as semiconductor ecosystem people, will experience this decade. Seriously this is exciting stuff and one of the top search terms on SemiWiki for 6 months running. Here is a quick peek at what the top EDA companies will be talking about at the Common Platform Technology Forum next month and yes it is all about FinFETs:

Joseph Sawicki, Vice President and General Manager of Mentor’s Design to Silicon Division, will be co-presenting with GLOBALFOUNDRIES in a keynote on the role of EDA in advanced manufacturing. He will focus on the increasing need for EDA tools and methods that optimize physical designs in order to mitigate manufacturing risks that grow at each successive process node due to the increasing impact of variability. Joe will show some examples of how collaboration between Mentor and Common Platform foundries has solved challenges at 28 and 20nm, and will highlight some current areas of effort related to FinFET and upcoming nodes. He will also touch on new approaches to accelerate the ramp to volume yield using advanced statistical techniques applied to production test data. Joe is a great guy, very approachable, and somebody you should network with if at all possible.

In the Mentor booth they will be discussing and demonstrating the unique Calibre DRC+ and DFM Scoring solutions for GLOBALFOUNDRIES. We’ll also be showing the latest in filling technology at 28/20nm based on Calibre SmartFill, and we’ll be describing advances in IC reliability checking and the specific checks offered by the Common Platform based on Calibre PERC.

Also read: Introduction to FinFET Technology Part I

Synopsys and Common Platform are collaborating to deliver innovative solutions including industry-leading FinFET enablement, high-performance core implementation and silicon-proven IP for Common Platform processes that help enable customers to achieve their design and performance goals. At the 2013 Common Platform Technology Forum, attendees can visit Synopsys’ booth #402 to learn more about their FinFET technology collaboration with Common Platform. In the afternoon technical session, Antun Domic, senior vice president and general manager of Synopsys’ Implementation Group, is co-presenting with Samsung on the topic of “Advances in 14-nm FinFET Process and Manufacturing.”

Cadencewill present the next-generation EDA technology for 14nm and FinFETs, including topics such as double patterning, lithography, and analytical modeling for this new process technology. Cadence will also discuss the results from the IBM-ARM-Cadence Cortex-M0 and Samsung-ARM-Cadence Cortex-A7 tapeouts on 14nm/FinFET technology. The presentation will be in conjunction with IBM’s perspective on innovative next-generation device structures being researched in IBM and partner labs. Additionally Cadence will present its broad and high quality IP and Verification IP (VIP) portfolio including the high performance DDR and PCIe IP.

Common Platform Technology Forum 2013

Date:
Wednesday, February 5, 2013

Location:
Santa Clara Convention Center
5001 Great America Parkway
Santa Clara, CA 95054

General Agenda:

[TABLE] style=”width: 100%”
|-
| 8:30am – 9:00am
| style=”width: 20px” |
| style=”width: 80%” | Registration and Continental Breakfast
|-
| 9:00am – 11:30am
|
| Keynote Session
|-
| 11:30am – 1:00pm
|
| Lunch / Exhibit Area Open
|-
| valign=”top” | 1:00pm – 4:40pm
|
| Technical Session
|-
| 4:40pm – 6:00pm
|
| Reception
|-

Exhibit Hours:
11:30am – 6:00pm

Attire:
Business casual