IROC Introduces an Upgraded Solution for Soft Error Analysis and Mitigation #61DAC

#61DAC Is the place to go for the latest ideas, technology and products for semiconductor design and manufacturing. Between the exhibit floor and the technical program, you can get a vast education on almost any topic. In this post, I will focus on a unique company and a new version of a unique solution. IROC Technologies specializes in helping the semiconductor industry evaluate and manage reliability risks during chip design to minimize soft errors over the life of the design. Advanced semiconductor processes make circuits more sensitive to soft errors and the growing use of these circuits in reliability-critical applications demands protection against glitches of all kinds. Here are some useful details from the show floor where IROC introduces an upgraded solution for soft error analysis and mitigation.

What’s New and Why It Matters

I recently covered a critical part of the technology portfolio from IROC – TFIT.  This tool delivers a best-in-class transistor/cell level soft error simulator. It essentially performs a comprehensive analysis of the circuit and particle interactions to determine if there is a potential for soft errors to occur. What is unique about the software is that it runs models using a standard SPICE simulator. Other approaches require 3D TCAD simulators which are hard to setup and run slowly, so TFIT makes detailed analysis of circuits much more accessible since it runs 100X faster than TCAD simulators. Partnerships with major foundries also ensure accurate results.

As discussed in the prior post, TFIT can be used to calculate the SER of basic cells and helps optimizing the layout of radiation hardened designs.. Once a system is built with these  basic cells, the next question to answer is how resilient the overall system is to soft errors. IROC’s SoC Failure in Time (SoCFIT) addresses this challenge, and a new version of the tool was announced at #61DAC.

SoCFIT and Its Role in Soft Error Analysis and Mitigation

I was fortunate to be able to spend some time at the IROC booth with Dr. Maximilien Glorieux, the CTO at IROC. Max has been a key driving force for tools like SoCFIT, so it was a very informative discussion. Max began by explaining that SoCFIT essentially provides the next level of analysis after TFIT.

The tool embeds a fault simulator, but it’s not like the ones used for test coverage that most of us are familiar with. These products inject faults (typically stuck at one or zero) into a circuit to see if a set of test vectors will find the fault. After applying the test vectors, if the output of the faulty circuit is different from the good circuit, that fault is deemed to be “covered”. 

Max explained that SoCFIT was doing a different kind of analysis. In this case, faults from single event upsets are injected into the circuit and the focus is on how these glitches propagate through the circuit. Many don’t propagate and so don’t represent high risk. But some do, and those logic paths must be fortified with approaches such as redundant logic and arbitration circuits to monitor the outputs of the redundant elements. If there is a discrepancy, the faulty data is filtered-out, and the back-up copies are used.

Protecting the whole SoC is an expensive process in terms of area and power, so a tool like SoCFIT is critical to ensure only the risky areas of the system are treated. The tool coordinates and analyzes a large amount of information about the system as shown in the graphic at the top of this post. Max explained that this work helps meet stringent functional safety standards by identifying critical circuit weakness from the earliest stages and throughout the design cycle.

Some of the features of SoCFIT include:

• Comprehensive error propagation analysis: evaluates fault propagation based on circuit structure and simulation vectors
• Detailed vulnerability reporting: computes logical (LDR), temporal (TDR), functional (FDR) de-rating/vulnerability factors
• Broad design language support: compatible with SystemVerilog, Verilog, and VHDL, fitting seamlessly into existing workflows
• Scalable for large designs: handles over 1 million flip-flops per partition, bottom-up approach makes it ideal for even the most complex SoC
• Ultra-fast simulation: achieves over 1,000X faster simulations than typical approaches, drastically reducing analysis time
• Extensive reporting: generates detailed reports highlighting the contribution of each cell, module, and instance to the overall FIT rate
• Efficient mitigation strategies: provides clear guidelines for mitigating vulnerabilities, helping you develop robust and reliable designs

Max went on to describe the features of the newest release of SoCFIT, that includes FDR FastSIM, an ultra-fast fault propagation simulation engine. This capability allows an efficient functional de-rating analysis about 1,000 times faster than conventional methods. Max also mentioned that the tool is designed to integrate seamlessly into the whole digital design flow, significantly improving end-product reliability by mitigating transient fault threats early. Its advanced features and speed make it ideal for handling complex SoC designs, maintaining accuracy and efficiency throughout the process.

To Learn More

I came away from my visit with Max knowing a lot more about what IROC can do for a wide range of designs, and why the work they are doing is so important. If high-reliability operation is important in your design work, you should learn more about how IROC can help. You can get an overview of how IROC fits into many markets here. And you can get more details on SoCFIT here.  And that’s how IROC introduces an upgraded solution for soft error analysis and mitigation at #61DAC.