In early 2000s, semiconductor design at RTL level was gaining momentum. The idea was to process more design steps such as insertion of test and other design structures upfront at the RTL level. The design optimization and verification were to be done at the RTL level to reduce long iterations through gate level design because changes at gate level led to re-work in the design from RTL to gate.
In 1997, Dr. Chouki Aktoufinitiated the implementation of a unique idea for DFT (Design for Testability) verification earlier in the overall design cycle. This work was done at National Polytechnic Institute of Grenoble (INPG) in France. The team worked extensively with a large number of European semiconductor companies to establish the proof of concept for the unique DFT technology and its benefits. It took more than 18 man-years of work to implement this concept. The new DFT technology improved the throughput of DFT design by a large extent.
In 2003, Defacto Technologies was founded with the spin-off of the team at INPG. Dr. Aktouf assumed the role of CEO and partnered with Michel Oger, Philippe Duchene, and James Girand in seeding the initial capital for founding Defacto Technologies in Grenoble, France.
Later, they received venture fund from CM-CIC Capital Innovation and Innovacom, two major investment companies in France. Also, French government supported Defacto’s initiative.
In 2005, Defacto introduced RTL Design for Test solution through which designers could do DFT exploration including test compression, memory/logic BIST and JTAG, and signoff at the RTL level. The RTL DFT could quickly check the quality of DFT design at block, IP and SoC levels.
In the pursuit of providing a complete design platform at RTL level, Defacto developed a number of tools to optimize and verify a design, and produce the synthesis-ready RTL. The design signoff at RTL level provided better predictability, design quality, and turn-around-time.
In 2008, the STAR – RTL Build & Signoff platform was launched as Defacto’s flagship fully-customizable RTL-to-RTL editing and verification platform that helped designers to complete planning, analysis, insertion, optimization, and debugging for designs at RTL level before submitting the final RTL to synthesis tool.
The RTL Design Builder could restructure a RTL and generate new RTL code which was optimized and simplified. The new RTL code could be easily synthesized into gate-level design which could be processed through downstream tools very smoothly.
The other tools added in the STAR RTL platform were RTL Design Checker which checked complete connectivity of the design with simulation-free pin-to-pin tracing, and RTL Low Power which checked for compliance of the RTL against UPF and suggested possible corrections for mismatches. Also, the RTL Low Power checked the power domain structures and generated RTL and UPF according to the defined power strategy.
All these tools were seamlessly integrated together within a common easy-to-use GUI. Also, Padring, a GUI based tool which enabled PAD placement was integrated with the STAR RTL platform. The RTL for a padring could be easily edited and generated after its verification.
For IP integration in SoC, RTL IP Integration was developed as a layer on top of RTL Design Builder and RTL Design Checker. The RTL IP Integration enabled integration, packaging, documentation and reuse of an IP based on the IPXACT format. The tool could automatically generate IPXACT description for a RTL block, IP or SoC. Also, it could parse an IPXACT description and check its coherency with the corresponding RTL design.
The STAR RTL platform provided a comprehensive environment for RTL optimization, connectivity check, power intent check, clock verification, ECO, SoC integration, and RTL signoff.
During 2008-10 timeframe the semiconductor community was recognizing the benefits of design signoff at RTL level. As the STAR RTL platform accelerated design closure, it was adopted by top communication chip companies and IDMs around the world. There were a significant number of design houses in US who used STAR RTL platform.
In 2013, Defacto celebrated its 10[SUP]th[/SUP] anniversary by opening its fully owned subsidiary, Defacto Technologies, Inc in Silicon Valley to provide enhanced support to its customers in US.
Defacto also expanded its operation in Japan to address the needs of Asian customers. Recently Socionext Inc, a major semiconductor company headquartered in Japan adopted Defacto solution for RTL and gate-level design analysis and building. Socionext is using Defacto’s STAR RTL platform in design development for various segments such as communication and multimedia. They are gaining 20 to 50 times reduction in design cycles by using STAR RTL platform.
Today, Defacto has their sales and support offices in multiple countries including Europe, US, China, Japan, Taiwan, South Korea, Singapore, and Israel.
The RTL Build & Signoff platform is much enhanced for doing automated design partitioning and restructuring at the RTL level. The platform can accommodate RTL, gate, or RTL-gate mixed level design editing and structuring which enhances SoC design productivity. A quick design exploration can be done at the RTL level to set the goals for an SoC. Also, the platform provides various APIs for designers to quickly access desired design information. Complex designs with hundreds of millions of instances can be easily processed on STAR RTL platform. The platform is generic for development of any kind of SoC or IP.
Over the years, Defacto Technologies has emerged as a provider of innovative design solution at RTL level that leads to increased design performance, reduced die size and power requirement, and improved design quality for better reliability.