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Tackling Layout Gradient Effects in 16 nm FinFET using Layout Automation

Tackling Layout Gradient Effects in 16 nm FinFET using Layout Automation
by Daniel Payne on 07-10-2015 at 12:00 pm

My first exposure to automating IC layout was back in the 1980’s at Intel where I coded a layout compiler to auto-generate about 6% of a graphics processor chip. The need to use automation for IC layout continues today, and with the advent of FinFET technology there are some new challenges like layout gradient effects that impact yield. I just finished viewing an archived webinar on this topic from experts at TSMC and Cadence, and will summarize what I learned about layout automation.

Captain Liu from TSMC started out and talked about the challenges of FinFET technology for custom IC design, like:

  • Increased complexity in layout design rules
  • Layout pattern effects

    • Layout-dependent effect
    • Density gradient effect
    • Self-heating effect
  • Running circuit simulation without layout effects

The approach engineered at TSMC required close collaboration with Cadence to address these challenges and it uses transistor-level layout generators called ModGens. Here’s the flow starting with schematic capture where the circuit designer sets up constraints like identifying a differential pair of transistors, running pre-layout circuit simulation including LDE effects, then creating layout automatically with a ModGen that understands density checking.

TSMC has created a device array API that reads technology-specific information from the PDK, runs DRC checks, and is aware of all the layout-dependent effects plus density checking. Instead of manually laying out FinFET transistors, you are running a ModGen instead to create devices that are correct and automated. Circuit designers either manually or automatically select transistor configurations in the schematic such as:

  • Differential pair
  • Stack series
  • Cascode

Related – Cadence’s New Implementation System Promised Better TAT and PPA

Next, through a GUI you fill out a form about how the array of transistors will be automated. Finally, the array layout is automated and will be DRC clean by design including features like:

  • Guard rings
  • Dummy devices
  • Matching devices
  • Density adherence
  • Pin shapes

Once you have the layout, then a back-annotation step will update your simulation netlist for the most accurate final simulation step.

This automated approach saves valuable engineering time by both reducing the number of circuit simulations required, and reducing the number of DRC/LVS runs to get a clean layout for custom designs.

Related – In-Design DFM Signoff for 14nm FinFET Designs

Jeremiah Cessna and Khaled ElGalaind from Cadence went into more details on how the ModGen device array library works. A ModGen is kind of like a P-cell plus it has the technology to do routing and checking. A screenshot from Virtuoso using a ModGen to implement a differential pair shows how the user fills in various options to control the custom layout:

There are over a dozen options for the circuit designer to work with. The automated IC layout for this differential pair including guard ring takes just a second or two to generate a clean layout:

In the live demo they changed parameters and viewed the layout results very quickly.

Layout generators available for the TSMC 16FF+ process include:

  • Differential pairs
  • Cascodes
  • Stack of series devices
  • HiR resistors
  • Coming soon

    • Current mirrors
    • Cross-coupled devices
    • Varactors
    • Decaps

Related – How ST Designs with Layout Dependent Effects (LDE)

These two companies have been working together for the past 18 months on this custom automation flow for the 16FF+ node. The 10nm node is also being automated in a similar fashion. Why continue using a manual IC layout flow for custom design, when you can speed things up with less effort using ModGens tuned for TSMC.

View the complete 16 minute archived video here.


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