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Signoff Summit: The Fastest Path to Design Signoff

Signoff Summit: The Fastest Path to Design Signoff
by Daniel Nenni on 11-13-2013 at 8:00 pm

Cadence’s Signoff Summit will be held next week, November 21 at Cadence in San Jose.

 This is the first of a series of all-day Signoff Summits from Cadence that focus on the multiple facets of design signoff. This first summit will include keynote addresses plus sessions covering the multiple solution components that comprise a comprehensive signoff solution:

  • Power analysis and signoff
  • Parasitic extraction
  • Digital timing closure and signoff
  • Physical verification
  • Design for Manufacturing (DFM)

There will be extended focus on the new Cadence® timing and power signoff solutions: Tempus™ and Voltus™. The Tempus Timing Signoff solution, announced in May 2013, generated huge attention at DAC. Voltus is a new Power Signoff solution that raises the bar for power analysis and signoff.

In each session, you will learn more details about the solutions and hear experiences directly from customers. For timing and power signoff, there will also be on-stage demos to show you in detail how these solutions perform.

To close the summit, there will be a cocktail hour from 5pm to 6pm. Silicon Signoff and Verification R&D technical staff will be on-hand to answer your detailed questions, plus additional demos will be shown.

Who should attend?

  • Design engineers responsible for timing closure and signoff
  • Design engineers responsible for power analysis and signoff
  • Design/CAD engineers interested in learning about advancements in signoff solutions
  • Project managers interested in learning how the latest Cadence signoff solutions can be used to improve their design methodology

What you will learn

  • The latest information on each of the signoff component solutions
  • How each of the solutions can improve your design flows and methodology
  • Practical usage of the signoff solutions directly from customers
  • Live demos of all solutions

Agenda
[TABLE] cellpadding=”5″ style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; margin-top: 5px; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid”
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| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; width: 100px; border-collapse: collapse; background: #eee; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Time
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; background: #eee; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Title
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; background: #eee; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Speaker
|-
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 8:30 AM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Breakfast/Registration
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” |
|-
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 9:00 AM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Cadence Welcome, Overview and Keynote
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Anirudh Devgan, Corp VP & Chief Technology Advisor
|-
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 9:30 AM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Defining Signoff amidst the EDA-Foundry-Design Vortex
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Richard Trihy, Golbalfoundries
|-
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 9:50 AM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Break
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” |
|-
| rowspan=”2″ valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 10:00 AM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Power Analysis & Signoff Challenges
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Jerry Zhao, Cadence
|-
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | High Performance, multi-CPU Scalable Power Signoff for Mega Designs
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Patrick Sproule, NVIDIA
|-
| rowspan=”2″ valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 11:30 AM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Fast and Accurate Signoff Extraction for Advanced Node Designs
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Kyle Peavy, Texas Instruments
|-
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Incremental Signoff Metal Fill Flow Using Encounter, PVS & QRC
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Takeyoshi Ikeda, Cadence
|-
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 12:15 PM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Lunch
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” |
|-
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 1:10 PM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Teething Signoff – You have to own it
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Jim Hogan, EDA Visionary & Investor
|-
| rowspan=”2″ valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 1:30 PM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Breaking the High Performance Barrier in Timing Analysis & Signoff – The Tempus[SUP]TM[/SUP] Timing Signoff Solution
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Ruben Molina, Cadence
|-
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Advanced Timing Solutions & Challenges – Statistical OCV, Path-Based Analysis, & Low Voltage FinFET modeling
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | R&D, Cadence
|-
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 3:00 PM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Break
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” |
|-
| rowspan=”2″ valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 3:15 PM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Transitioning to PVS
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Marie Luo, Conexant Systems
|-
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Physical Verification Signoff for DDR IP using PVS
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Tobing Soebroto, Cadence IP Design
|-
| rowspan=”2″ valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 4:00 PM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Macro Modeling based Layout Dependent Effect-Aware Custom Design Flow
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Pei Yao, Globalfoundries
|-
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Foundry-certified DFM services: A alternative to meet mandatory DFM requirements
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Cadence DFM Services
|-
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | 5:00 PM
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Close and Reception
| valign=”top” style=”border-bottom: #ccc 1px solid; border-left: #ccc 1px solid; border-collapse: collapse; border-top: #ccc 1px solid; border-right: #ccc 1px solid” | Lip-Bu Tan, Cadence President & CEO
|-

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