In EDA we have come to expect that only small start-up companies create new tools, however a team at Cadencehas developed a new IC power integrity tool called Voltus from scratch. To learn more I spoke last week with KT Moore, a Group Director at Cadence. I’ve known KT for over a decade, and first met him when he was at Magma marketing their FineSIM circuit simulator.
KT Moore, Cadence
This new EDA tool is used for IC Power Integrity with both static and dynamic analysis techniques.
- Full-chip power analysis (leakage, switching, internal)
- Full-chip power grid analysis (IR drop, electro migration checks)
- Power & IR drop impact on design closure (static timing, package and board)
- Integrates with Static Timing Analysis (STA) using the Tempus tool (massively parallel).
- Integrates with Board and package analysis using the Sigritytools.
The dominant player is Apache for power integrity, and Voltus will go head-to-head against their tools.
Voltus is mostly a chip-designer tool. Run this type of tool during IC design, then again at sign-off.
Why Another Power Analysis Tool
Existing tools are running out of steam. The run times are slowing, while the number of power domains requiring analysis are increasing. One question that needs to be asked, is: How does power integrity effect timing closure?
Voltus can be up to 10X faster in performance by using multi-core processors, and scaling across a network. You can choose to run the tool hierarchical or flat. On a 400M instance design you would use hierarchy to complete the analysis in a reasonable time. The capacity is up to 1B instances, more than enough for today’s SoC projects.
The accuracy of Voltus is good enough to get it foundry certified, but you’ll have to stay tuned for an official announcement. Expect SPICE-like results from Voltus because it extracts the RC grid accurately and knows about instance power distribution.
Design closure is improved because you can run Voltus for an early power-grid analysis while in implementation, not having to wait until sign-off. Both chip and the system can be co-designed using Voltus plus Sigrity tools.
This tool works in any EDA tool flow because it reads standard file formats, or it can be run in an all-Cadence tool flow.
Power or Timing tools could be run separately, however they are really dependent upon each other. The simultaneous analysis approach of Voltus and Tempus for power and timing is something new, and speeds up closure while improving accuracy in the STA tool by up to 3%.
You can use Voltus to analyze:
- Early rail analysis
- Power gate switching
- Chip + Package + PCB co-simulation (thermal analysis, and 3D IC support like CoWoS)
Once you’ve run the analysis an engineer still has to figure out what to change, and then make the change to the layout of the IC, package or board.
Who is Using It
The first two public customers of Voltus are Freescale and IDT.
The Cadence press release has quotes from each of these companies.
Cadence has announced two new EDA tools this year, Tempus for STA and now Voltus for power sign-off. The Voltus tool is production ready, and your evaluation could take about 6 to 8 weeks of time.
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