Webinar: Design Methodologies for Next-Generation Heterogeneously Integrated 2.5/3D-IC Designs

I had the opportunity to preview the upcoming SemiWiki webinar titled: Design Methodologies for Next-Generation Heterogeneously Integrated 2.5/3D-IC Designs. John Park’s message, describing this powerful Cadence solution, really impressed me. That’s why I want to encourage you to register for it and join this SemiWiki webinar on Thursday, April 23, at 10 am PDT. You’ll get in-depth information about how Cadence makes planning, design and verification of next-generation heterogeneously integrated 2.5/3D-ICs and wafer-level packages cost-effective, easier and faster.

Our customers value the semiconductor industry for its fast pace of innovation as well as for providing better and cheaper solutions for an ever-broader range of – often heterogeneous – applications. A well-coordinated design and manufacturing supply chain, with domain experts at every stage, is the basis for all these accomplishments. Dozens of recent announcements of heterogeneously integrated 2.5/3D-IC designs, primarily from larger companies, have demonstrate how well heterogeneous integration can improve performance per Watt and increase functionality in a single IC package. However, until now, the high development cost, resource requirements and long development times have stopped many engineers from using these powerful solutions for bringing their ideas to market.

That’s a very familiar scenario to me. During my ASIC years, (1980 to 2000) I saw our design center engineers working 80+ hour weeks to meet tape-out schedules for, in today’s view, really small designs. How did our industry get from then 10 Million gate designs to today’s up to 10 Billion gate solutions – a 1000 x improvement?

The short answer is: AUTOMATION!  In more depth: This level of improvement was only possible, because TSMC and other wafer manufacturers developed, together with their Electronic Design Automation (EDA) partners, process design kits (PDKs). They specified exactly what the process technologies were capable of and what was not allowed. This PDK data (e.g. libraries, SPICE decks, design rules, layer information, etc.) enabled their mutual customers to accurately simulate what’s technically feasible and quickly iterate to improve performance and/or reduce unit cost of a design. Over time, design tools and methodologies became more user-friendly, managed larger design complexities and drove reducing cost per function. In addition to more powerful EDA tools, the initially very simple library elements became more and more complex building blocks and, available as verified soft IP (RTL code) or silicon-proven hard IP (GDSII), they simplified and accelerated ASIC design even further.

Back to the webinar. John Park will outline why and how Cadence, in cooperation with the big assembly and test houses (a.k.a. OSATs) and IC packaging experts at wafer foundries, developed a design environment for heterogeneously integrated 2.5/3D-ICs and wafer-level packages. Cadence is also simplifying the use of chiplets (silicon proven hard IP, implemented in bare die) as design-productivity enhancing building blocks.

In my view, the biggest advantage of the Cadence multi-die IC solution is that it links their proven and well-known design tools for IC, package and board (Innovus^R, Virtuoso^R, Allegro^R), uses OrbitIO^R and other proven tools, as well as recently introduced tools (e.g. Clarity^R) to plan, design and verify your 2.5/3D-ICs. This Cadence solution will enable you to quickly become productive as developer of heterogeneously integrated 2.5/3D-ICs and wafer-level packages.

Please use this opportunity, register here and view this SemiWiki webinar replay.  A link to the replay will be sent to all registered people in case you miss it or want to review it again. It’s time well spent… Herb