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Cadence and Green Hills Share More Security Thoughts at ARM Techcon

Cadence and Green Hills Share More Security Thoughts at ARM Techcon
by Randy Smith on 10-15-2019 at 10:00 am

On Wednesday, October 9, 2019, I had the pleasure of spending the day at ARM Techcon at the San Jose Convention Center. In the morning, in addition to getting some sneak peeks into the exhibitor area, I attended some of the morning keynote presentations, which focused on artificial intelligence (AI) and machine learning (ML) topics. Those were great presentations and a special thanks to the ARM marketing team for the high-end production value. Next, I was off to see some of the technical sessions, giving me a chance to get back to my EDA and verification roots.

I attended a joint presentation by Frank Schirrmeister of Cadence and Joe Fabbre of Green Hills titled, Pre-silicon Continuum for Concurrent SoC, Software Development and Verification for Safety and Security Critical Systems. At the Cadence Automotive Summit just this past July 30th, I also saw a presentation from Dan Mender, Green Hills Software’s VP, Business Development called Addressing the State of Safety and Security in Today’s Autonomous Vehicles System Designs. These two presentations have demonstrated to me just how serious these two companies are about working together to solve the critical requirement of system security. You can see my blogs from the Cadence Automotive Summit here and here.

One common message from both presentations is the simple theme that you cannot have safety if you do not also have security. The point is that no matter how much you work on safety, a system that is vulnerable to a malicious attack, will not remain safe. This concept applies to all types of systems, not just automotive. Working with Cadence and Green Hills allows a system architect to utilize security measures in both the hardware and software design. One nugget I saw in the presentation was the theme shared by both companies to simplify architectures, specifically, “Separation of critical components with an emphasis on simplicity for critical components is key.”

As we all know, the earlier you find a design flaw, security gaps, and other bugs, the less expensive it is to fix. This perception increases the importance of two concepts – Hardware/Software Co-Verification, and Virtual Platforms. These are areas where Cadence has succeeded and has a thorough product portfolio to support its customers.

As the diagram above shows, several different techniques can be applied to co-verification as we move through the different design stages. You will find the largest number of bugs at the beginning of the design process, and the rate of finding bugs should decrease over time. But these later bugs are still important as they may not show up until the design process reaches its more refined stages. Test coverage and test suites will also get more thorough in time, and you will want to use these tests at the most refined version of your system available at that time. The full range of Cadence verification products can solve that for you.

The presentation also reviewed some of the technology integration points as they are developed and optimized through the Cadence collaboration with Green Hills. For instance, the Green Hills Hypervisor and RTOS technology Integrity – focused on safety and security – can run on the Cadence dynamic verification engines. The software is compiled using safety-aware, certified compilers, and it can be debugged using the Green Hills Multi IDE, which is connected via standard interfaces like JTAG. As an example integration, a virtual platform using Arm Fast Models was shown to boot Linux and get debugged using the Green Hills Multi IDE.

The earlier you can do software development, the more time you will have to find and fix bugs – and security flaws are just that, bugs! Being able to run software testing on virtual platforms rather than waiting for functional silicon is a huge benefit. You will only be able to find some security flaws when running software on a model of the hardware or the hardware itself. Cadence’s Virtual System Platform enables you to start testing your software long before RTL or prototypes of the hardware are available. The virtual system platform can be combined with other parts of the Cadence  System Development Suite, such as Cadence’s emulation and prototyping products, to give you a fast, reliable environment for doing early software development and validation.

This session was one of several very useful presentations at ARM Techcon. If you missed it this year, make sure to put it on your schedule for next year. If you sign up to be notified when ARM TechCon 2020 registration opens, ARM will give you a $100 discount on the regular price of an All-Access conference pass for the 2020 event.