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May 16, 2013June 14, 2019 by Daniel Nenni

Cadence Technical Sessions @ #50DAC (Free Food!)

Cadence Technical Sessions @ #50DAC (Free Food!)
by Daniel Nenni on 05-16-2013 at 10:00 am
Categories: Cadence, EDA

Cadence is a DAC anchor, everyone will visit their booth, so lets look at their technical sessions and put our agendas together. Lets start with the breakfast/lunch sessions because Cadence usually puts out quite a spread, we all gotta eat and free food tastes even better:

Has “Timing Signoff Innovation” Become an Oxymoron? What Happened and How Do We Fix It? Lunch
In this panel fielded by leading-edge technologists and venture capitalists, we will discuss the technology advances, or lack thereof, in the area of timing signoff. Timing signoff and closure is becoming the largest pole in the design flow tent with the increase in MMMC timing analysis views, lack of integrated signoff closure tools, and increasing variation factors. Each panelist will provide their insight into what’s needed from the EDA industry, academia, and users to ensure that innovation keeps pace with design needs.

The Cadence System-to-Silicon Verification Breakfast
Join us for a free breakfast to learn how next-generation system and SoC verification offerings from Cadence accelerate your system integration and reduce time to market. Learn about the newest capabilities of the Cadence System Development Suite, including Virtual System Platform virtual prototyping, Incisive® advanced verification, Palladium® acceleration and emulation, Rapid Prototyping Platform FPGA-based prototyping, and the Verification IP catalog, which adds new communication protocols and now supports acceleration and emulation. Listen to discussion about the latest methodologies for advanced verification and example applications from key Cadence customers. Be sure to bring your toughest questions for our experts panel.

Next lets look at the in-depth technology and methodology presentations targeted at creating the highest-quality silicon chips, systems-on-chip devices, and complete systems at lower costs. Sessions include the latest in signoff, mixed signal, low power, RTL-to-GDSII, custom, functional verification, verification IP, system development and hardware-software integration, high-level synthesis, PCB, and IC packaging:

lang: en_US

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