WP_Term Object
(
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 514
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 514
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
)
            
14173 SemiWiki Banner 800x1001
WP_Term Object
(
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 514
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 514
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
)

Cadence Technical Sessions @ #50DAC (Free Food!)

Cadence Technical Sessions @ #50DAC (Free Food!)
by Daniel Nenni on 05-16-2013 at 10:00 am


Cadence is a DAC anchor, everyone will visit their booth, so lets look at their technical sessions and put our agendas together. Lets start with the breakfast/lunch sessions because Cadence usually puts out quite a spread, we all gotta eat and free food tastes even better:

Has “Timing Signoff Innovation” Become an Oxymoron? What Happened and How Do We Fix It? Lunch
In this panel fielded by leading-edge technologists and venture capitalists, we will discuss the technology advances, or lack thereof, in the area of timing signoff. Timing signoff and closure is becoming the largest pole in the design flow tent with the increase in MMMC timing analysis views, lack of integrated signoff closure tools, and increasing variation factors. Each panelist will provide their insight into what’s needed from the EDA industry, academia, and users to ensure that innovation keeps pace with design needs.

The Cadence System-to-Silicon Verification Breakfast
Join us for a free breakfast to learn how next-generation system and SoC verification offerings from Cadence accelerate your system integration and reduce time to market. Learn about the newest capabilities of the Cadence System Development Suite, including Virtual System Platform virtual prototyping, Incisive® advanced verification, Palladium® acceleration and emulation, Rapid Prototyping Platform FPGA-based prototyping, and the Verification IP catalog, which adds new communication protocols and now supports acceleration and emulation. Listen to discussion about the latest methodologies for advanced verification and example applications from key Cadence customers. Be sure to bring your toughest questions for our experts panel.

Next lets look at the in-depth technology and methodology presentations targeted at creating the highest-quality silicon chips, systems-on-chip devices, and complete systems at lower costs. Sessions include the latest in signoff, mixed signal, low power, RTL-to-GDSII, custom, functional verification, verification IP, system development and hardware-software integration, high-level synthesis, PCB, and IC packaging:

[TABLE] style=”width: 100%”
|-
| style=”width: 100%” | [TABLE] border=”1″ cellpadding=”5″ style=”margin-top: 5px; border-collapse: collapse”
|-
| valign=”top” style=”width: 80px” | June 3, 2013
| align=”center” valign=”top” style=”font-weight: bold; background-color: #dedede” | Suite 1
| align=”center” valign=”top” style=”font-weight: bold; background-color: #dedede” | Suite 2
|-
| style=”font-weight: bold; background-color: #dedede” | 10:00 AM
| 3D-IC Design Methodology Trifecta
| Incisive Debug Analyzer Cuts Debug Time from Days to Minutes
|-
| style=”font-weight: bold; background-color: #dedede” | 11:00 AM
| Advanced Strategies for Implementing Power-efficient GHz+ ARMv7 Cortex®-A Processor-Based SoCs
| Multi-substrate SiP/2.5D-IC Planning
|-
| style=”font-weight: bold; background-color: #dedede” | 12:00 PM
| A Complete, Silicon-validated 20/16/14nm Solution Using Encounter and Virtuoso
| System Development Suite: Verification Computing Platform (Palladium XP)
|-
| style=”font-weight: bold; background-color: #dedede” | 01:00 PM
| Low Power Verification of Mixed-signal Designs
| Sigrity Chip-Package-Board IO-SSO Analysis
|-
| style=”font-weight: bold; background-color: #dedede” | 02:00 PM
| Advanced Implementation Techniques for Mixed-signal Designs
| LP Simulation: Are You Really Done?
|-
| style=”font-weight: bold; background-color: #dedede” | 03:00 PM
| Cadence Timing Solutions
| Netlist Handoff: Manage Complexity and Lower Design Risk By Qualifying Your Front-End Design Before
|-
| style=”font-weight: bold; background-color: #dedede” | 04:00 PM
| Power Format Update: Latest on CPF and IEEE 1801 (UPF)
| System Development Suite: Virtual System Platform Connected Virtual Prototyping
|-
| style=”font-weight: bold; background-color: #dedede” | 05:00 PM
| Cadence Qualified Signoff Down to 16nm
| Speed Design Project Turnaround with C-to-Silicon Compiler and Multi-level Verification
|-

|-

REGISTER HERE [TABLE] style=”width: 100%”
|-
| style=”width: 100%” | [TABLE] border=”1″ cellpadding=”5″ style=”margin-top: 5px; border-collapse: collapse”
|-
| valign=”top” style=”width: 80px” | June 4, 2013
| align=”center” valign=”top” style=”font-weight: bold; background-color: #dedede” | Suite 1
| align=”center” valign=”top” style=”font-weight: bold; background-color: #dedede” | Suite 2
|-
| style=”font-weight: bold; background-color: #dedede” | 10:00 AM
| Reducing the Verification Loop for Custom Design
| Accelerating Embedded Software Development with FPGA-Based Prototyping
|-
| style=”font-weight: bold; background-color: #dedede” | 11:00 AM
| Cadence Timing Solutions
| Sigrity Chip-Package-Board IO-SSO Analysis
|-
| style=”font-weight: bold; background-color: #dedede” | 12:00 PM
| Cadence Qualified Signoff Down to 16nm
| Netlist Handoff: Manage Complexity and Lower Design Risk By Qualifying Your Front-End Design Before
|-
| style=”font-weight: bold; background-color: #dedede” | 01:00 PM
| Advanced Strategies for Implementing Power-efficient GHz+ ARMv7 Cortex®-A Processor-Based SoCs
| Can Your Spreadsheet Do This —- Innovative Applications of Pre-RTL Chip Planning
|-
| style=”font-weight: bold; background-color: #dedede” | 02:00 PM
| 3D-IC Design Methodology Trifecta
| Multi-substrate SiP/2.5D-IC Planning
|-
| style=”font-weight: bold; background-color: #dedede” | 03:00 PM
| Updated Spectre Platform: Improving Your Verification Throughput
| Speed Design Project Turnaround with C-to-Silicon Compiler and Multi-level Verification
|-
| style=”font-weight: bold; background-color: #dedede” | 04:00 PM
| A Complete, Silicon-validated 20/16/14nm Solution Using Encounter and Virtuoso
| System Development Suite: Verification Computing Platform (Palladium XP)
|-
| style=”font-weight: bold; background-color: #dedede” | 05:00 PM
| Foundation IP Characterization
| Reduce Verification Time By Up to 60%. Proven
|-

|-

REGISTER HERE [TABLE] border=”1″ cellpadding=”5″ style=”margin-top: 5px; border-collapse: collapse”
|-
| valign=”top” style=”width: 80px” | June 5, 2013
| align=”center” valign=”top” style=”font-weight: bold; background-color: #dedede” | Suite 1
| align=”center” valign=”top” style=”font-weight: bold; background-color: #dedede” | Suite 2
|-
| style=”font-weight: bold; background-color: #dedede” | 10:00 AM
| Advanced Strategies for Implementing Power-efficient GHz+ ARMv7 Cortex®-A Processor-Based SoCs
| System Development Suite: Verification Computing Platform (Palladium XP)
|-
| style=”font-weight: bold; background-color: #dedede” | 11:00 AM
| Mixed-signal Verification
| LP Simulation: Are You Really Done?
|-
| style=”font-weight: bold; background-color: #dedede” | 12:00 PM
| Reducing the Verification Loop for Custom Design
| The Best of Both Worlds – FPGA-Based Prototype + Virtual Prototype Enables Early System Integration
|-
| style=”font-weight: bold; background-color: #dedede” | 01:00 PM
| Cadence Timing Solutions
| System Development Suite: Virtual System Platform Connected Virtual Prototyping
|-
| style=”font-weight: bold; background-color: #dedede” | 02:00 PM
| A Complete, Silicon-validated 20/16/14nm Solution Using Encounter and Virtuoso
| Netlist Handoff: Manage Complexity and Lower Design Risk By Qualifying Your Front-End Design Before
|-
| style=”font-weight: bold; background-color: #dedede” | 03:00 PM
| 3D-IC Design Methodology Trifecta
| Can Your Spreadsheet Do This —- Innovative Applications of Pre-RTL Chip Planning
|-
| style=”font-weight: bold; background-color: #dedede” | 04:00 PM
| Successful RTL-to-GDSII Low-Power Design
| Sigrity Chip-Package-Board IO-SSO Analysis
|-
| style=”font-weight: bold; background-color: #dedede” | 05:00 PM
| Custom/AMS Design at Advanced Nodes
| Multi-substrate SiP/2.5D-IC Planning
|-

REGISTER HERE

lang: en_US

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