Mixed-Signal SoC verification has integrated solution

These days when we talk of SoC verification, what comes to our mind immediately is VirtualPlatform. Of course with the increasing size, complexity and different styles of designs, it is very much a need.

However, that is supported by actual verification engines and methodologies which are varying considerable with digital, analog and mixed-signal portions of the design. Gone are the days when we used to embed pre-verified analog block into digital design with identified signals interfacing between them. Conversely, digital blocks were imported into analog centric designs. Today, we have large analog, digital and mixed signal design content, all sitting together in an integrated design and interacting with multiple signals continuously. And almost in all designs, mixed-signal content is inevitable.

Typically, analog components are simulated by Spice and its variants and digital simulation is simplified by discrete data models simulated through Verilog or VHDL simulators. As design complexity has increased along with the need of analog and digital components staying together, various methodologies, languages and tools have emerged for modelling and verifying analog, digital and mixed-signal designs with trade-off between accuracy and performance/capacity.

Verilog-A, Verilog-AMS, VHDL_AMS, SystemVerilog and now SystemC (extended to
SystemC AMS for system level mixed signal modelling) provide tremendous capabilities to model analog and digital content together which can be efficiently simulated by a standard tool having single kernel in optimum time and desired level of accuracy. Cadence provides a suite of tools and techniques applicable in various contexts to solve this challenging problem of verifying complete SoC mixed-signal design. It provides a seamless environment with unified GUI which integrates its simulation engines, design environment and verification methodologies together to provide a unique experience to the user. I came across a white paper of Cadence which describes the verification solution with nice level of details. The white paper can be found at –
http://www.cadence.com/rl/Resources/white_papers/ms_soc_verification_wp.pdf

As an example Virtuoso AMS Designerlinks Virtuoso custom design platform with Incisive verification platform. It supports simulators like Spectre and Spectre RF Circuit Simulators, UltraSim Full Chip simulator, Accelerated Parallel Simulator and Incisive Enterprise Simulator; all integrated together in common GUI and used as per need.

For interface and translation between discrete levels of digital signals and continuous voltage levels of analog signals is done automatically through special connection modules. Common Power Format (CPF) is used with novel techniques to distinguish between a functional error and a false error due to power shut down in a particular digital or analog portion of the circuit (which usually is a case with low power design to save power that advocates to keep power ON only for active circuitry at a time). Again provisions for levels of abstractions from behavioural up to transistor level have been provided.

Just a glimpse of how the digital centric and analog centric methodologies are being unified has been represented as –

To sum it up, while Spice simulators help in verifying individual analog IP blocks, as we move up towards full chip verification of mixed signal SoCs, analog behavioural models embedded with digital languages and the techniques and tools associated with them provide up to 100x speed up in the complete SoC verification.