Mixed-Signal design is one of the very initial design methodologies, pioneered by Cadence with its lead in custom design; now taking centre space in the world of SoCs. Its growth is surmountable as it finds its place in most of the high growth electronics like smart phones, automotive applications, networks and communications, bio-medical engineering, safety and security applications, precise instrumentation etc. With the increase of design size having large analog content along with digital, shrinking technology node, power becoming critical and timing as ever overwhelming, the complexity of design and verification has increased tremendously.
There is an opportunity to learn about the latest mixed-signal methodologies and techniques from the experts in this domain from Cadence and how it provides the complete solution for the mixed-signal design. It’s a forum where one can build network with other technologists as well that can, at times, help meeting the challenges of this complex task.
It’s a complete one day session, here is the program:
[TABLE] style=”width: 100%”
| style=”width: 12%” | Date:
| style=”width: 50%” | 02 Apr 2013 – 09 Apr 2013
| Ottawa, Ontario – April 2, 2013
Baltimore, MD – April 4, 2013
Chelmsford, MA – April 9, 2013
| Register »
Who should attend?
- Circuit designers
- AMS and SoC verification engineers
- Analog/custom layout engineers
- Digital P&R engineers
- CAD engineers and managers
- Design managers
- Anyone involved with realizing mixed-signal designs in silicon
What is there to learn?
- Techniques and tips to enhance your mixed-signal flow
- Insight into the latest mixed-signal verification and implementation methodologies
- Recommendations, based on silicon-proven successes, for effectively deploying new methodologies in your design environment today
- Modeling analog behaviour with highly effective real number models
- Applying assertion-based, metric-driven verification
- Verifying low-power intent with dynamic and static methods
- Floorplanning and integrating designs in a seamless, OA-interoperable flow
- Analyzing timing and power for complex SoCs to prevent silicon re-spins
For one to gain true confidence, the session includes success stories from Cadence in terms of case studies. Also, IBM’s presence will be there with its latest technologies as foundry partner along with world class process design kits which enable high productivity and faster turn-around-time. It’s a day worth spent!! Register »
Complete details about the agenda can be found at –
Any question about this event?
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