Using Linting to Write Error-Free Testbench Code

In my job, I have the privilege to talk to hundreds of interesting companies in many areas of semiconductor development. One of the most fun things for me is interviewing customers—hands-on users—of specific electronic design (EDA) tools and chip technologies. Cristian Amitroaie, CEO of AMIQ EDA, has been very helpful in introducing me to both commercial and academic users of his company’s Design and Verification Tools (DVT) Integrated Development Environment (IDE) family of products.

Recently, Cristian connected me with Lars Wolf, Harald Widiger, Daniel Oprica, and Christian Boigs from Siemens. They kindly shared their time with me to talk about their experiences with AMIQ’s Verissimo SystemVerilog Linter.

SemiWiki: Can you please tell us a bit about your group and what you do?

Siemens: We are members of a 10-15 person verification team at Siemens and part of a department that does turnkey development of application-specific integrated circuits (ASICs) for factory automation products within the company. Our team of experts focuses on verification IP (VIP), developing new VIP components and also reusing and adapting existing VIP.

SemiWiki: What are your biggest challenges?

Siemens: We have all the usual issues of any project, such as limited resources, tight schedules, and increasing complexity. But there are two specific challenges that led us to look at Verissimo as a possible solution.

First, since our VIP can be used by many projects, we have a very high standard of quality. We don’t want our ASIC design teams debugging problems that turn out to be issues in our VIP, so we must provide them with error-free models, testbenches, and tests. Of course, the better the verification environment, the better the ASICs that we provide to the product teams.

The second challenge involves the extension of our development landscape to incorporate SystemVerilog and the Universal Verification Methodology (UVM) for our projects. At the time, many of our engineers were not yet experts in this domain, so we were looking for tools that would help them learn and help them write the best possible code.

SemiWiki: So, you thought that a SystemVerilog/UVM linting tool would help?

Siemens: Yes, we were looking specifically for such a solution. The whole point of linting is to identify and fix errors so that the resulting code is correct. We believed that the engineers would learn over time to avoid many of these errors and make code development faster and smoother. We considered several options and ended up choosing Verissimo from AMIQ EDA.

SemiWiki: What was the process for getting the team up and running with the tool?

Siemens: It’s built on an IDE, so it’s easy to use and it provides all sorts of aids in navigating through code and fixing errors. Most engineers used it successfully after minimal training. We spent much of our effort refining the linting rules checked. Verissimo has more than 800 out-of-the-box rules, and some were more important to us than others. We started with the default ruleset and then turned off the checks that we didn’t need for one reason or another. We ended up with about 510 rules enabled. Every rule must be explainable and understandable by every verification engineer.

SemiWiki: Is this ruleset static?

Siemens: No; we meet regularly to review the rules and to consider adding new ones since AMIQ EDA is always offering more. On average, we add four or five rules every month. We try to keep up with new rules and new features in Verissimo so we’re always getting the maximum benefit for our team.

SemiWiki: Are there any particular rules that impressed you?

Siemens: We know that a lot of the rules were added due to user demand, and in general we also find these rules very useful. There are some rules that cover aspects of SystemVerilog that we hadn’t previously considered, such as detecting dead code, identifying copy-and-paste code, and pointing out coding styles that may reduce simulation performance. We were especially intrigued by the random stability checks. Initially we took reproduction of random stimulus for granted, but we learned that it doesn’t happen without proper coding style.

SemiWiki: How is Verissimo run in your verification flow?

Siemens: We encourage our engineers to run linting checks as they write their code, but we do not require them to do so. We considered making a linting run a requirement for code commit, but we didn’t want engineers to consider waiving possible errors just to get through the check-in gate. We require the flexibility to commit code that may not yet be perfect but is needed to get the testbench to compile and run regressions.

We decided instead to make Verissimo part of our daily regression run. Using a common ruleset ensures consistency in coding style and adoption of best practices across the entire team. Verissimo results are included in our regression dashboard and tracked over time, along with code coverage and pass/fail results from regression tests. Any linting errors and error waivers are discussed during code reviews as part of making the VIP as clean and reusable as possible.

SemiWiki: Do you see any resistance to linting among your engineers?

Siemens: We honestly didn’t know what to expect in this regard, and we have been pleasantly surprised. We have a small, cohesive team and there is no debate over using linting as part of our process. There is also no abuse of error waivers, which are reviewed carefully and used only as a last resort.

SemiWiki: Has Verissimo lived up to your expectations?

Siemens: It certainly has addressed the two challenges that led to us looking for a linting solution: high quality and coding guidance. We now have confidence that our VIP is lint error-free, with no syntax or semantic errors, and compliant to our coding rules. Our VIP is more reusable, maintainable, and manageable. Verissimo has also proven to be a very good learning tool. As we discuss rules and debug linting errors, we understand both SystemVerilog and UVM better, and we think more deeply about our code.

SemiWiki: How has your experience been working with AMIQ EDA?

Siemens: It’s more of a partnership than a pure vendor-customer relationship. Early in our engagement, we compared our coding guidelines with the Verissimo rules, and asked AMIQ EDA to add some new rules plus adjustments and new parameters for some existing rules. Of course, as with any piece of software, we’ve found a few bugs in the tool itself. In all cases, we have found them to be responsive and supportive.

SemiWiki: Do you plan to change the way that you use Verissimo in the future?

Siemens: Since we have been successful so far, we plan to continue everything we are doing now on all new VIP projects. There are two areas where we would like to improve a bit. Our goal was to meet every two weeks to discuss linting rules, errors, and waivers, but we haven’t always done that. We would like to make those meetings more regular. We would also like to update Verissimo releases more often throughout the project so that we can take advantage of new rules that require new capabilities in the tool.

SemiWiki: Gentlemen, thank you very much for your time. It is great that you have had so much success with adding linting to your testbench and VIP development flow.

Siemens: It has been our pleasure.