Verification of Multirate Systems with Multiple Digital Blocks

Our popular smart phones have a whole slew of RF-based radios in them for: Bluetooth, WiFi, LTE, GSM, NFC. Using just a single clock frequency for a DSP function or SoC is a thing of the past, so the design of multirate systems is here to stay. So now the challenge on the design and verification side is to use a methodology that supports:

• Multiple levels of design abstraction
• RF blocks and digital blocks interacting
• Multirate simulation together with HDL simulation

Co-simulation Approach

The idea of co-simulation has been around for decades, and in this approach you would combine a system level simulator with an HDL simulator using an API:

Such an API between the system level and HDL levels would have to:

• Produce results that are repeatable and consistent
• Provide high performance
• Be easy to setup and use
• Convert data (i.e. Fixed point, floating point)
• Allow models to be switched between algorithm and HDL levels
• Support interactive debugging features

One huge technical hurdle is that HDL simulators are built with an event-driven architecture, while system level simulators use a data flow architecture. You could kludge together a multirate co-simulation using multiple instances of an HDL simulator to account for different clock rates like this:

This approach is not tenable because of: the added license costs, inefficient use of memory while simulating, distributed debugging and usability.

The Aldec Approach
Since necessity is the mother of invention, Aldec has engineered a co-simulation approach called COMRATE, which stands for COnsistent Multi RATE, and it avoids the previous list of pitfalls:

So, with COMRATE you are using a single license of the HDL simulator while it’s co-simulating with a system level simulator. The first use of COMRATE is to co-simulate between Aglient SystemVue and Aldec Riviera-PRO. The SystemVue tool has both an RF simulator for doing spectral analysis, plus a data flow simulator for designing and verifying algorithms.

A Modulator Example
Let’s say that you wanted to design a simple modulator system. The system schematic in SystemVue has a carrier and input sources (circles), multiplier (blue subsystem), interpolation (arrow-shaped block) and gain block (green subsystem).

Two-rate system example

The single time domain simulation results for the two HDL blocks (blue, green) are displayed in Riviera PRO:

A third sampling rate module (pink) can be added to this example:

With the default settings in COMRATE this example will trigger an error message about negative delta time, because SystemVue is looking at the current and next time stamps and noticing time going backwards. To fix this error you need to enable the multirate data flow co-simulation mode in SystemVue. Now you can see the correct simulation results from both simulators:

Co-simulation results in the multirate data flow mode

White Paper

Arkadiusz Golec from Aldec has written a 16 page White Paper that has complete details of how Agilent and Aldec developed the COMRATE engine to connect two simulation environments: System level simulation and HDL simulation. This co-simulation enables design and verification of RF-based SoC designs in less time.

lang: en_US