Aldec Delivers Leading Verification Methodologies!

For those of you who don’t know, Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, ASIC Prototyping, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.

I first met Aldec at DAC and was very impressed by the focus they have on training and education. You can find a nice list of white papers HERE, multimedia webinars, videos, and demonstrations HERE, application notes HERE, and tutorials HERE. And of course the Aldec SemiWiki landing page is HERE with coverage by Daniel Payne and Don Dingee.

Aldec has an important DO-254 Training Event (Webinar)coming up that we are all invited to:

DO-254 Verification Strategies

Date:Thursday, February 21, 2013
Time:11:00 AM – 12:00 PM PST
Presenters:
Louie DeLuna – Aldec DO-254 Program Manager
Daniel Conway – X-Tek DO-254 Consultant

Abstract:
As a best-practice standard, efficient ASIC and FPGA project planners will allocate 1/3 of the project cycle to design and 2/3 of the project cycle to verification. The best of these planners will bias toward even more verification-hours and innovative verification strategies whenever possible, because the great reality of schedule-time allocated to verification is that THERE’S NEVER ENOUGH TIME.

When an FPGA or ASIC is destined for an avionics product, effective design of that DO-254-qualified device is even more dependent-upon good verification strategies and practices. Good verification strategies will use those precious hours more effectively – and will also consistently prove to be more useful when combined with a comprehensive exploitation of well-written requirements and compliance with a well-constructed verification process, planned in advance of the work.

REGISTER HERE

In this webinar, we will discuss various verification strategies and how they can be applied to successful verification of a design in a DO-254 Levels A/B flow.

Agenda:

• How and where verification fits into the overall process
• Verification Strategies
• Ad-hoc testing
• Directed testing
• Constrained random testing
• Verification Architectures
• Driver – Waveform
• Auto-checking
• OVM/UVM
• Code coverage and its proper usage
• Documentation and reviews
• Test plan vs. test cases
• How to pass the audit
• Q & A

Aldec is a proven EDA solutions provider delivering leading verification methodologies that support the latest language standards enabling their customers to grow while leveraging evolving technologies. Definitely worth a look, their corporate website is HERE.

RTCA/DO-254 and EUROCAE/ED-80 are means of compliance for the development of airborne electronic hardware containing FPGAs, PLDs and ASICs. FPGA design and verification under DO-254 guidelines is a rigorous undertaking, and requires special features and capabilities from design, simulation and hardware verification tools.