Since 1978 I’ve seen many trends in the semiconductor design world: transistor-level IC design, gate-level design, RTL coding, High Level Synthesis (HLS) and IP re-use. We’ve witnessed the growth in design productivity enabling chips starting with just thousands of transistor all the way up to billions of transistors by using newer design paradigms and more advanced process nodes, like 14 nm FinFET in production now. One EDA company focused on HLS and low power design has an interesting story to tell at the upcoming DAC conference and exhibit in June by inviting NVIDIA, Qualcomm and Samsung to talk about their hands-on experiences. Calypto is the company, and I’ve just chatted with Mark Milligan to get a preview of what’s to come at DAC.
Related – Verifying the RTL Coming out of a High-Level Synthesis Tool
FinFET transistors have been all the rage ever since Intel started talking about tri-gate a few years back, and since then we’ve seen foundries like TSMC, Samsung and GLOBALFOUNDRIES all provide FinFET processes to designers. Leakage power is reduced in FinFET technologies, but on the flip-side there’s an increase in dynamic power that needs to be dealt with during design. On the EDA methodology side you can consider using a tool like PowerPro from Calypto to:
- Support multiple use case scenarios in creating low-power RTL
- Exploring RTL alternatives for low-power
- Guided or automated optimization using formal equivalency proofs
- Get quick and early RTL power analysis at both block and chip levels
Register online for:
Samsung is my favorite smartphone company and I love the long battery life on my Galaxy Note 4 device and large 5.7″ display. You’ll want to hear how Samsung engineers used a power optimization flow that included formal verification with SLEC pro, and had lint, CDC and autocheck compliance.
Register online for: Samsung: RTL Design Flow with Dynamic Power Optimization for Mobile SoCs
Qualcomm has been using both high-level synthesis and high-level verification (HLV) on their image processing IP. Engineers are now using a standardized HLS/HLV design and verification flow. Chips used for smartphone applications have been successfully designed with this new methodology.
Register online for: Qualcomm – Designing ASIC IP at Higher Level of Abstraction
NVIDIA is a well-known leader in all things related to graphics chips. They first evaluated then adopted HLS and HLV for their TEGRA mobile processors. Come and find out how they moved from a traditional RTL flow to an HLS/HLV flow to accelerate both the design and verification processes.
Register online for: NVIDIA – High Level Synthesis
There are also a couple of tutorials that you can sign up for at DAC that can answer your detailed questions about what the learning curve is like when using C and SystemC as a design language:
- Is C++ or SystemC the Right Language for your next HLS Project?
- Building an iDCT for H.265 Using Catapult
Related – Shorten the Learning Curve for High Level Synthesis
The second tutorial on building the iDCT (Inverse Discrete Cosine Transform) will walk you through algorithm coding practices, optimization steps, and how to achieve the best QoR. You should attend this tutorial if you’ve never used an HLS approach before, and be sure to ask lots of questions to get clarification.
Summary
RTL coding had its place in history, and now is the time to consider moving up to HLS and HLV to accelerate both design and verification of your next SoC. DAC is an incredible place to learn about these technologies, and find out how they would fit into your flows.
Related – HLS, Major Improvement through Generations
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