Very recently, I was seeing intense discussions on the need for agile hardware development just like agile software and ideas were being sought from experts as well as individuals. While in software world it has already evolved, in hardware world it’s yet to see the shift in paradigm. My point is that the end goal of agile hardware development must be to accomplish maximum of the hardware job at the highest level of abstraction at the fastest rate which should leave only essential jobs (which may be done in parallel) to be done at lower levels till physical implementation and that must improve the turnaround time by a large extent. Also, I am a believer of the future standing on the shoulders of the past and hence we must look at what has been done so far for hardware realization. These thoughts reoccurred in my mind when I came across a webinarwhich dealt with writing C++ code for High Level Synthesis (HLS) which can be much simpler to write and easier to test and debug than RTL code and obviously orders of magnitude (1000x – 10000x) faster in simulation compared to RTL; of course actual timing and cycle accuracy need to be looked at later.
Although, the webinar does not tell anything about agile, my intuition is that this methodology of hardware realization through software writing in C++ (most versatile programming language) must be looked at in the spirit of agile development for hardware; of course further exploration about actual hardware realization and how these concepts can be used to be truly agile is a matter of research. Let’s look at some details about this methodology; courtesy Calypto.
The key aspect here is to use algorithmic model of hardware without any timing which could later become reference model for hardware. The algorithmic model uses AC (Algorithmic C) data types (can be used with SystemC as well) which is bit-accurate, has unlimited length integer, fixed-point and floating-point that enables very fast simulation as well as compile and link times. Refinement of the model can be done by converting it to fixed-point model. Standard C++ debuggers and test coverage tools can be used along with assertions.
Above is an example code fragment of ALU implementation with ‘assert’ and ‘cover’ point statements to realize coverage driven verification of the implementation. This ALU function can be easily synthesized by Catapult, Calypto’s HLS tool. The algorithmic model can be wrapped with SystemC/TLM, embedded in SystemVerilog/UVM environment and dumped onto ESL platform for SoC verification.
The hardware architecture refinement such as block partitioning (through function calls), memory architecture (synthesized directly without any re-ordering from source code) and processing order depending on the data movement must be defined in the source code. Synthesis constraints such as clock period, technology, resource sharing, throughput etc. are for consideration at RTL, not for algorithmic model.
Above is an example of JPEG engine created by partitioning the algorithmic model; each box represents a function which is mapped to hierarchy during synthesis.
The synthesizable C++ models thus created can be used for design exploration with ‘what if’ analysis, SystemVerilog testbench development with SystemC wrappers, sequential logic equivalence checking, formal property checking and TLM synthesis.
What lies at the core of HLS is, mapping of abstract transaction to pin-accurate, cycle-accurate protocol and optimizing of throughput and latency in the target technology.
As shown above, by developing an executable design in C++ (or SystemC), the overall flow is condensed by a large extent compared to traditional flow for hardware design. One can simulate the functionality in the code very fast and then apply constraints to optimize the design through HLS; any architectural change again can be quickly implemented in the source code. Also any derivative design (such as cell phone to tablet) with similar function but different constraints can be quickly done. Power analysis and optimization can also be done with shorter loops between RTL and C++.
The SLEC (Sequential Logic Equivalence Checker) is a unique tool that can formally verify C++ against optimized C++, C++ against RTL and also check C++ properties, where it can formally prove if assertions always hold, something simulation may miss. Thus SLEC along with Catapult unlocks the full potential of ESL by providing optimized and verified RTL from C++ / SystemC. The RTL block can be verified in UVM environment against reference and ESL model.
A well executed methodology in this way can reduce RTL design and verification time by more than 50%, re-use HLS source code in TLM SoC model and leverage verification environment across abstractions. More detailed information can be obtained by registering and attending the webinarat Calypto’s website.
Coming back to my thought (it might appear radical) about agile hardware development – Can a pure agile system be thought of where RTL level stuff can also be done at the functional level in algorithmic model? Can the concepts used in SLEC, Catapult and may be other HLS tools applied at more micro as well as macro level to make it cycle accurate at algorithmic level? By the way, I learnt that SLEC also handles timing differences in internal computation and at interfaces. Comments welcome!Share this post via: