Gary Smith published a list of what to see at DAC, and I noticed that he listed DOCEA Power in a category of ESL Thermal. I’ll be meeting the DOCEA engineers on Wednesday at DAC to learn more about their two newest ESL products:
- Thermal Profiler
- Power Intelligence
In general DOCEA Power tools allow you to manage power and thermal analysis at the ESL level, which is a higher level of abstraction than RTL or gates. This ESL approach can:
- Save 40-70% on power consumption by early power architecture exploration
- Secure your specification and avoid design re-spins
- Improve power and thermal budget tracking all along the design
- Speed up power and thermal management software validation and debug
deFacto Technologies and DOCEA are making a joint presentation on Monday, June 2 at 5PM in Room 258/260:
- Joint design flow to fill the gap between architecture and RTL during low-power design exploration
Pascal Vivet from CEA-LETI is presenting in Session 16 of the Design Track on Tuesday, June 3 from 10:30AM – 12:00PM in Room 105:
- Thermal Modeling Methodology for Fast and Accurate System Level Analysis. Application to a Memory-on-Logic 3D circuit.
On Thursday, June 5 at 9AM to 5PM in Room 202 there’s a workshop:
You can visit DOCEA at DAC in booth #2223, and look for my blog next week. To schedule a DAC meeting, use this online form.
Docea Power develops and commercializes a new generation of methodology and tools for enabling faster more reliable power and thermal modeling at the system level. Based on its Aceplorer platform, the Docea Power solutions use a consistent approach for executing architecture exploration and optimizing power and thermal behavior of electronic systems at an early stage of any electronic design project. The company is headquartered near Grenoble, France, and in San Jose, CA, and has sales and application support offices in Japan and Korea.
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