hip webinar automating integration workflow 800x100 (1)
WP_Term Object
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 3903
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 3903
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0

IP Reuse and Management in Monterey!

IP Reuse and Management in Monterey!
by Daniel Nenni on 04-08-2014 at 10:30 pm

 One of the benefits of being part of SemiWiki is building relationships with a wide variety of companies covering every semiconductor design application imaginable. We are blessed, absolutely. Another benefit of being part of SemiWiki are the invitations to attend, participate, and even organize events such as EDPS. Last year I organized FinFET Day which was a huge success. This year I organized IP Day with a keynote from Martin Lund of Cadence and presenters from eSilicon, Arteris, IPextreme, Mentor, and Atrenta. Unfortunately we had a speaker cancellation so I asked ClioSoft to step in and they graciously accepted.

Design management (DM) is one of the applications that I had not been familiar with before SemiWiki but have grown to respect thanks to ClioSoft. ClioSoft was one of SemiWiki’s first subscribers and today they are the model of success for emerging companies. Looking at their landing page you will see dozens of blogs on every aspect of DM including customer experiences from semiconductor companies big and small. Design Reuse and IP Management is an integral part of DM and Ranjit Adhikary from ClioSoft will be explaining in more detail what that means exactly and where it is heading.

If you look at the Semiconductor IP usage trends over the last five process nodes (65nm, 40nm, 28nm, 20nm, 16nm) the number of unique IP per tape-out is increasing while the ability to re-use IP across nodes is dropping. And thanks to the ultracompetitive mobile market with new products coming at us every day, design cycles are incredibly short and complex. Design Reuse and IP Management is critical to our success moving forward so this is a workshop you do not want to miss:

The Electronic Design Processes Symposium (EDPS) provides a forum for a cross-section of the top thinkers, movers and shakers who focus on how chips and systems are designed to discuss state-of-the-art electronic design processes and CAD methodologies. The workshop focuses on the improvement of the overall design process, rather than on the functions of the individual tools themselves.

Featuring the following 2014 Keynote Speakers:

  • Chris Lawless – Director, Intel
  • Wally Rhines – CEO, Mentor Graphic
  • Martin Lund – SVP, Cadence

Program includes the following sessions:
Thursday 4/17 Sessions 8:00AM -5:45 PM

  • Design Flow Challenges (including Panel)
  • Pre-Silicon SW Development Platforms
  • Technology Updates – FinFET, 3D-IC, FD-SOI

Thursday 4/17 Dinner Keynote 6:30PM
Wally Rhines, CEO, Mentor Graphics

Friday 4/18: IP Day 8:00AM-3:00PM

  • IP Integration, Design, Reuse (Session)
  • IP Verification and Qualification (Session)

Program includes engineers and key executives from the following companies:
Altera, Intel, Synopsys, Cadence, ClioSoft, Mentor, eSilicon, Atrenta, and more…

See www.eda.org/edps, to see the detailed Program, Registration information, and news/review of this event. When registering use Promo Code: SemiWikiGofor $50 off

This Symposium will be held at the www.montereybeachresort.com.

More Articles by Daniel Nenni…..

lang: en_US

Share this post via:


There are no comments yet.

You must register or log in to view/post comments.