Mapping SysML to Hardware Architecture

The Systems Modeling Language (SysML) is used by systems engineers that want to specify, analyze, design, verify and validate a specific system. SysML started out as an open-source project, and it’s a subset of the Unified Modeling Language (UML). Mirabilis Design has a tool called VisualSim Architect that imports your SysML descriptions so that you can start to measure the actual performance of an electronic system before the software gets developed by choosing an optimal hardware configuration, knowing that requirements and constraints are met very early in the system design process, before detailed implementation begins. I attended their most recent webinar and learned how this system level design process can be used to create a more optimal system that meets metrics like power, latency and bandwidth.

Tom Jose was the webinar presenter from Mirabilis where he has done R&D and now is the Lead Application Engineer. The first case study presented was a media application system with a camera, CPU, GPU and memory components where the power target was under 2.0W, and the number of frames analyzed in 20 ms had to be over 50,000.

The first approach was to run all of the tasks in software using the A53 core, without any acceleration, which resulted in the power goal met, however the peak frame rate wasn’t met. Analysis revealed that the rotate frame step was taking too long, so a second approach using hardware acceleration was modeled. With HW acceleration the frame rate reached 125.5K frames, but power was too high. For the third iteration some power management was applied to the HW accelerator block, and then both frame rate and power metrics were fully achieved.

For a second case study Tom showed an automotive example where AUTOSAR was running on an ECO while faults were being injected.

When faults were injected into the simulation then memory became corrupted, causing spurious runnable execution. Failures also increased the system latency, while keeping ECU activity high. Normal execution could be quickly compared versus execution with injected faults.

The benefit of using VisualSim Architect is that a systems engineer can find the right hardware components early in the exploration phase, eliminating surprises during implementation. This Mirabilis approach bridges the gap between concept and implementation, so once your requirements are defined you can explore different architectures, optimize for performance and power, or even inject faults to see the consequences. Engineers can model the software, network and hardware components rather quickly in this GUI-based simulation platform. There’s already an extensive system-level library of IP models, allowing you to drag and drop to model your system.

A final example showed a Radar system that started out as SysML blocks, then imported into VisualSim architect for exploration, analysis and optimization.

The RADAR simulation was run, but reading the activity results showed that requirements were not being met. By sweeping some of the system-level parameters and re-running a few dozen simulations, a table of passing and failing requirements was generated. The system architect could then choose which of the passing cases to use.

Summary

Mirabilis started out in 2003 and over the past 20 years has grown to include development and support centers in the USA, India, Taiwan, Japan and Czech Republic. The VisualSim Architect tool enables a systems engineer to visualize, optimize and validate a system specification prior to detailed implementation. This methodology produces a shift-left benefit by shortening the time required for model creation, communication and refinement, and even implementation.

View the 28 minute webinar recording on YouTube.

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