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WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 3596
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 3596
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
)

Atrenta Seminars in Asia – Making RTL Signoff Real

Atrenta Seminars in Asia – Making RTL Signoff Real
by Daniel Nenni on 08-18-2013 at 8:10 pm

Engaging with the semiconductor ecosystem is critical to surviving in the fast paced times we work in. Face to face interaction at all levels is key and semiconductor IP is a prime example. How do you ensure that your IP meets objective quality requirements before integration into your SoC, and that your SoC is ready for handoff to the back-end implementation?

RTL Signoff is here. A growing number of design teams rely on Atrenta’s RTL platform to certify their IP choices and ensure their designs are implementation ready. Adding a signoff flow at RTL provides them a competitive edge that can mean the difference between success and failure.


Atrenta’s SpyGlass Predictive Analyzer® significantly improves design efficiency for the world’s leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today’s consumer electronics revolution. More than two hundred companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. And with the addition of BugScope™ verification efficiency is also enhanced, allowing engineers and managers to find the fastest and least expensive path to silicon for complex SoCs.

Join us for a live seminar to learn more about RTL Signoff:[TABLE] cellspacing=”3″ style=”width: 410px”
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| style=”width: 50px” | 9:30 AM

| style=”width: 207px” | Arrivals & check-in

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| 9:50 AM
| Introduction of speakers
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| 10:00 AM
| Introduction to Atrenta, RTL Signoff and IP Kit
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| 10:45 AM
| How to get signoff confidence for CDC
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| 11:30 AM
| Verification signoff – using assertion synthesis
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| 12:15 PM
| Lunch & networking
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| 1:30 PM
| RTL power reduction and power signoff
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| 2:15 PM
| Timing is everything – getting constraints right
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| 3:00 PM
| Break
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| 3:15 PM
| How to simplify RTL restructuring
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| 4:00 PM
| Achieving quality goals – DFT at RTL
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| 4:45 PM
| Lucky draw & event conclusion
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Register todayas seating is limited for this FREE event:

[TABLE] style=”width: 400px”
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| style=”width: 200px” | Beijing, China
Sep 23, 2013
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| style=”white-space: nowrap; vertical-align: top” | Shanghai, China
Sep 25, 2013
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| style=”white-space: nowrap; vertical-align: top” | Hsinchu, Taiwan
Sep 27, 2013
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| Seoul, South Korea
Oct 02, 2013
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Register todayas seating is limited for this FREE event:

lang: en_US

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