As an applications engineer for over 15 years supporting physical design tools that enable implementation closure, I have seen the complexity of timing closure grow continuously from one process node to the next. At 28nm, the number of scenarios for timing sign-off has increased to the extent that is way beyond the number that a Place & Route tool can handle. Most designers turned to Static Timing Analysis (STA) tools for a solution. But the STA tools have two limitations:
- STA tools usually run in a scenario-by-scenario fashion. For STA tools to generate ECOs that close timing for all scenarios, one would need to run multiple sessions at the same time, one session for each scenario. This requires the STA tools to be run simultaneously on multiple servers, with each server needing a license.
- Current STA tools do not have or use the physical information. As a result, many ECO’s (Engineering Change Orders) generated by STA tools may end up being not implementable in the physical world due to placement and/or routing congestions.These limitations prompted for a new solution that can:
- Simultaneously handle large number of scenarios without requiring large number of licenses/server machines
- Understand the impact placement and routing have on those scenarios and hence implement ECO directive accordinglyThese requirements are critical to effectively and efficiently achieve timing closure.
Without these capabilities, designers are forced into not only a process that takes too many iterations and longer time to closure, and often have to accept lower chip performance for time to market.
In a recent customer engagement, I had to help the customer close timing on a design that was highly congested in both placement and routing. In addition, the design required timing closure on more than 100 sign-off scenarios. It would have taken multiple engineers and many weeks to close timing using an STA based methodology.
A key point to note is that not all routing congested areas are also placement congested, such as the channels between the macros at the top level of an SoC design. Hence, to effectively address timing violations, the tools and flow must understand both placement and routing congestion. Otherwise, one might cause new setup violations while fixing the hold violations due to detoured ECO routes. This is the primary reason why an STA based flow that is not placement and most importantly routing-aware takes many iterations to close timing.
We identified the congestion issues and used a placement and routing aware timing closure solution that could simultaneously handle all MMMC scenarios. Results: quicker timing closure with far fewer iterations!
At 20nm, a timing closure solution must be routing aware, because the additional requirements of double patterning and Vt implanting rules have a direct impact on timing and hence closure.
Welcome your comments and sharing your experiences with timing closure.
ICScape Inc. (Santa Clara, California) develops and markets solutions that accelerate SoC design closure. Its flagship products, ClockExplorer and TimingExplorer were released to the market in 2006 and 2009 respectively. They have been successfully used and taped-out in over 100 SoC designs. Other products from ICScape include PowerExplorer, RCExplorer and LibExplorer. It offers sales and technical support for its products in US, China, Japan, South Korea and Taiwan.