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Forte CEO on Design and Verification Complexity

Forte CEO on Design and Verification Complexity
by Daniel Nenni on 05-10-2013 at 9:00 am

Sean Dart’s first DAC (Las Vegas) was as a customer in 1989. Designs were hitting 15,000 gates back then so he was looking for better schematic editors and simulators for gate level design. Fast forward 25 years and Sean’s customers are doing 15,000,000 gate subsystems and that number is growing steadily every year. Unfortunately design schedules are not growing so again EDA is critical. By automating the generation of high-quality RTL code from high-level design descriptions, companies like Forte provide a way for designers to handle the increasing gate counts without increasing design schedules.

 Q: What are the specific design challenges your customers are facing?

The dimension that Forte addresses for our customers is that of complexity. Allowing designers to code models at much higher levels of abstraction allows them to deal with the complexity of both design and verification in a much more complete manner.

There is, of course, a productivity benefit in the initial creation of models (IP), but the most noticeable improvement comes through reuse. High-level IP is significantly more reusable (and retargetable) than RTL IP. This dramatically improves the value of that IP for our customers by both increasing the effective longevity of the IP and making it much cheaper (and more timely) to retarget in future designs.

Q: What does your company do?

Our flagship product is Cynthesizer, the number one SystemC-based high-level synthesis tool on the market. In the last few years we have also invested heavily in IP. This includes industry-leading fixed-point and floating-point IP which is shipped in tens of millions of consumer devices. We have also added a lot of IP in SystemC form, which is very high-level, retargetable and ready for use in your ESL flow. I believe that the industry will move to high-level IP in order to realize the gains offered by its flexibility and productivity gains.

Q: Why did you join your company?

I started out with Chronology in 1997 and was focused on verification. We merged with CynApps in 2001 to form Forte and the product direction moved to being more synthesis-focused. At that time, I was the VP engineering and became CEO in 2006.

The idea of building a high-level synthesis tool was intriguing to me and the concept of ensuring that verification was considered in the tool flow from the very ground up obviously fit my previous experience. This has proved to be one of the critical components leading to successful deployment of HLS in the marketplace. I am still very passionate about the technology and the continued growth in adoption of Cynthesizer is great motivation to continue down the path.

Q: How does your company help with your customers’ design challenges?

As I mentioned before, our products really help with the issue of design complexity. But it is not only about the core implementation tools. Forte has added a lot of supplementary IP that comes with the tool in order to help users get started more quickly. One example of this is the Interface Generator, which is a utility that allows users to quickly configure a number of complex interfaces and have full SystemC versions of those interfaces generated automatically.

Other non-core elements that are very important include tools to develop and debug your SystemC code and very complete training and kick-start materials and examples. This includes many white-papers, a complete online Knowledge Base, online instructional videos and detailed pre-canned examples and tutorials. Simply producing the best result from synthesis is not the only requirement. We have recognized that we need to work closely with new users to get them to the “expert” development level as quickly as possible, and these collateral materials are a critical element in that process.

Q: What are the tool flows your customers are using?

The Forte tool flow sits right on top of our customers’ existing RTL development flows. The input to the process is SystemC and the output is Verilog RTL that is then processed by all the major logic-synthesis tools and simulators. Forte provides complete methodology which includes integration and automation with those downstream tools to ease the path of adoption of Cynthesizer.

Q: What will you be focusing on at the Design Automation Conference this year?

We’ve widely been considered the industry standard for SystemC synthesis and this year we’re announcing the next generation of our Cynthesizer SystemC synthesis product – Cynthesizer 5.0.

Cynthesizer 5.0 is the culmination of several years worth of work to redesign our core synthesis platform from the ground up. We’ll be demonstrating the advantages of the new “C5” platform in terms ease-of-use, performance and quality of results.

Perhaps more importantly though, we are also introducing Cynthesizer Low Power, our low power synthesis product that utilizes the C5 platform and performs a number of low power optimizations directly in the Cynthesizer core – not as an RTL post-processing step.

We’re also rolling out our new ease-of-use products including a SystemC IDE called Cynthesizer Workbench and our new YouTube channel for customer education.

Q: Where can SemiWiki readers get more information?

We have a number of online resources to provide more information.

Our web site: www.ForteDS.com

Our YouTube channel, containing a number of instructional videos and demos:www.youtube.com/ForteDesignSystems

Our Facebook page:www.facebook.com/ForteDS

Our Blog: CynCity.ForteDS.com

And now our SemiWiki landing page:Forte on SemiWiki.com

Forte Design Systems™ is the #1 provider of electronic system-level (ESL) synthesis software, confirmed by Gary Smith EDA, provider of market intelligence for the global Electronic Design Automation (EDA) market. Forte’s software enables design at a higher level of abstraction and improves design results. Its innovative synthesis technologies and intellectual property offerings allow design teams creating complex electronic chips and systems to reduce their overall design and verification time. More than half of the top 20 worldwide semiconductor companies use Forte’s products in production today for ASIC, SoC and FPGA design. Forte is headquartered in San Jose, Calif., with additional offices in England, Japan, Korea and the United States. For more information, visit www.ForteDS.com.

lang: en_US

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