Architecture Exploration of Processors and SoC to trade off power and performance 5
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Are there enough FPGA tools?

Are there enough FPGA tools?
by Luke Miller on 05-09-2013 at 9:00 pm

Sometimes I send my boy to grab me a tool and hours later he comes back with the wrong one. The patient man that I am, I calmly explain what I mean and then the world is right once more. Believe that do ya?

As you know the world is flooded with tools, tools and more tools. We all have our ruts and favorite flows and such but given the huge FPGA densities here and now and the future will no doubt bring more mixed signal devices what is the right set of tools?

I had a nice phone call with an EDA company this morning and we agree with this observation. People are scared of FPGAs, and HLS is not being embraced. Why? Of all the tools out there, in my small opinion HLS is the best tool of the last decade. I’m really curious what is stopping you? My guess is big company politics. Sometimes tool flows are set by people that do not do the job. Ahhh the process police, watch out they are corrupt.

The other tool observation is that now and beyond, for FPGAs we cannot settle for spin, re-spin like a 100 times over; especially in simulation. We make our test benches, we make our test vectors for hardware, we tweak our chip scope etc… There is much time wasted on doing close to the same things over and over. We must get better at it and need to do it once or twice. The tools need to intelligently handle requirements change, as the requirements are written by women therefore we are not sure what they mean. Can you believe I just wrote that? My old job would have me in front of HR as we speak, and I would have to fake listen. So I leave this blog open ended, and here is the question?

Say I want you to design a function, a SINE function, Taylor series expansion, floating point at 100 MHz, 20 clock latency, FIFO in/out. From start to finish what is the flow you would use? I’m thinking we would have many different answers. I’ll share mine, MATLAB, then Vivado HLS in about 5 minutes. Then simulate once in ModelSim. Looking back, my tools preferences are based on what I was forced to use by the man. Being on my own is allowing me to actually find the best flow and I know that will deviate some but this I know; the way I do things and you do things is going to change if we want to stay competitive.

The upside for FPGAs is they are staying around for a while. GPUs and CPUs cannot compete with the deterministic low latency solution that the FPGA offers. We FPGA users can control every bit, so that’s good news for you control freaks. So please comment below and share what flow you use.

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