Sanjay Keswani founded Consensia in 2013. He has deep experience in the high-tech industry, guiding some of the world’s high profile technology brands through complex innovation and business transformation projects including companies such as Atmel, KLA-Tencor, Hughes Aircraft, and Motorola Mobility. Consensia customers… Read More
Webinar: Top Five Challenges Preventing Design Closure!
According to a recent engineering survey, completing IC designs on time and within specifications gets exponentially more challenging with each node. Why? Here are the top five reasons:… Read More
Lowering Costs for Custom SoC Development – ARM and Tanner EDA
Cost is a major barrier when an electronic design company starts to consider developing a custom SoC for a particular market segment. But what if there was a way to lower the development cost, or even get to an SoC proof of concept for no cost except of course for your engineering expenses? That value proposition caught my attention… Read More
Analyzing All of those IC Parasitic Extraction Results
Back at DAC in 2011 I first started to hear about this EDA company named edXact that specialized in reducing and analyzing IC parasitic extraction results. So Silvaco acquired edXact and I wanted to get an update on what is new with their EDA tools that help help you to analyze and manage the massive amount of extracted RLC and even K … Read More
How to Design a Custom SoC with Analog, webinar from ARM and Tanner EDA
Leading edge SoC designs can contain billions of transistors, cost over $10M to design, and take over 18 months to deliver, but not all SoCs require that much complexity, cost and time. In fact, there is a growing class of SoC designs that integrate the popular ARM Cortex-M0 processor along with analog blocks that work with sensors… Read More
Eclipsing IDEs
In a discussion with Hilde Goosens at Sigasi, she reminded me of an important topic, relevant to the Sigasi platform. Some aspects of technology benefit from competition, others less obviously so and some absolutely require standardization. Imagine how chaotic mobile communication would be if wireless protocols weren’t standardized.… Read More
Automotive OEMs Get Boost as NetSpeed NoC is Certified ISO 26262 Ready
I read with great interest today news from NetSpeed Systems that both their Gemini and Orion NoC IPs have been certified ISO 26262 ASIL D ready. They were certified by SGS-TUV Saar GmbH, an independent accredited assessor. This is a big deal as up till now, it was left up to the OEMs to do most of the heavily lifting to qualify their IC’s… Read More
Something New for Semiconductor Parametric Testing
The familiar maxim that “time is money” certainly typifies our semiconductor industry where the mass production of chips, boards and systems helps to power our global economy and ever-increasing standard of living. The foundries that manufacture chips have to ensure that the process technology is in fact producing… Read More
What You Don’t Know about Parasitic Extraction for IC Design
Out of college my first job was doing circuit design at the transistor-level with Intel, and to get accurate SPICE netlists for simulation we had to manually count the squares of parasitic interconnect for diffusion, poly-silicon and metal layers. Talk about a burden and chance for mistakes, I’m so thankful that EDA companies… Read More
SPICE Model Generation using Machine Learning
AI and machine learning are two popular buzz words in the high-tech daily news, so you should be getting used to hearing about them by now. What I hadn’t realized was that EDA companies are starting to use machine learning techniques, and specifically targeted at the daunting and compute intensive task of creating SPICE models… Read More